Table 10.5 Srctlx Receive Control Register Bits - Analog Devices ADSP-2106x SHARC User Manual

Bit(s) Name Definition
0 SPEN* SPORT Enable
1-2 DTYPE Data Type (data format, companding)
3 SENDN Serial Word Endian (1=LSB first)
4-8 SLEN Serial Word Length – 1
9 PACK Data Word Packing (16-bit to 32-bit)
10 ICLK Internally Generated Receive Clock
11 – reserved
12 CKRE Data, Frame Sync Sampling on Clock Rising Edge
13 RFSR* Receive Frame Sync Required
14 IRFS Internally Generated RFS
15 – reserved
16 LRFS Active Low RFS
17 LAFS* Late RFS
18 SDEN SPORT Receive DMA Enable
19 SCHEN SPORT Receive DMA Chaining Enable
20 – reserved
21 D2DMA* 2-Dimensional DMA Array Enable
22 SPL* SPORT Loopback (test)
23 MCE Multichannel Enable
24-28 NCH Number of Channels – 1 (multichannel operation)
29 ROVF** Receive Overflow Status (sticky, read-only)
30-31 RXS** RX Buffer Status (read-only)
11=full, 00=empty, 10=partially full

Table 10.5 SRCTLx Receive Control Register Bits

* Must be cleared for multichannel operation.
** Status bits are read-only. They are cleared by disabling the serial port (setting
SPEN=0). RXS may subsequently change state if the data is read or written by the
ADSP-2106x core while the SPORT is disabled.
The RXS status bits indicate whether the RX buffer is full (11), empty
(00), or partially full (10). To test for space in RX, therefore, test for
RXS0 (bit 30) equal to zero. To test for the presence of any data in RX,
test for RXS1 (bit 31) equal to one.
The Receive Overflow Status bit (ROVF) is set whenever new data is
received while the RX buffer is full; the new data overwrites the
existing data.
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Serial Ports 10
10 – 11