Figure 6.2 Dma Data Paths & Control - Analog Devices ADSP-2106x SHARC User Manual

Core
Internal Memory
Processor
PM Address Addr
DM Address Addr
Addr
IOA
PM Data
DM Data
I/O Address
17
Bus (IOA)
Internal DMA
Address Generators
Grants Requests
10 10
Internal DMA
Prioritizer
10
Requests
10
Grants
DMA Controller
* Note that link ports are not available on the ADSP-21061.
Figure 6.2 DMA Data Paths & Control
For external DMA requests, the ADSP-2106x includes the DMA
DMAR1
request inputs
DMAG1
outputs
external asynchronous peripheral devices. By pulling a
low and waiting for the appropriate
the ADSP-2106x, a simple I/O device can transfer data to ADSP-2106x
internal memory or to external memory.
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Data Data Data
PMD DMD IOD
I/O Data
48
Bus (IOD)
External Port
DMA FIFOs
EPB0 EPB1 EPB2 EPB3
(6-deep FIFO Buffers)
Link Port FIFOs
LBUF0 LBUF2 LBUF4
LBUF1 LBUF3 LBUF5
(2-deep FIFO Buffers)
Serial Port FIFOs
RX0 TX0
RX1 TX1
(2-deep FIFO Buffers)
Other IOP Registers
Direct Write FIFO
(6 deep)
I/O Processor
DMAR2
and , along with the DMA grant
DMAG2
and , to support DMA transfers to and from
DMAGx
DMA
External Port
PMA
DMA
PMD
DMD
Slave Write FIFO
EPD
(Async writes - 4 deep)
(Sync writes - 2 deep)
EPA
Buffer
Ext. Port Ext. Port
48 32
Data Bus Address
(EPD) Bus (EPA)
Ext. Port DMA
Address Generators
Requests Grants
4
4
Ext. Port DMA
Prioritizer
4
Requests
4
Grants
DMA Controller
Link Ports
Serial Ports
DMARx
line
signal to come back from
6
32
ADDR
31-0
48
DATA
47-0
DMAR1
DMAG1
DMAR2
DMAG2
LxDAT
3-0
DR0
DT0
DR1
DT1
6 – 3