Sport Dma Chaining - Analog Devices ADSP-2106x SHARC User Manual

Memory
Address Register Channel Number & Function
0x0060 II0 DMA Channel 0 – SPORT0 Receive
0x0061 IM0 DMA Channel 0 – SPORT0 Receive
0x0062 C0 DMA Channel 0 – SPORT0 Receive
0x0063 CP0 DMA Channel 0 – SPORT0 Receive
0x0064 GP0 DMA Channel 0 – SPORT0 Receive
0x0065 DB0 DMA Channel 0 – SPORT0 Receive
0x0066 DA0 DMA Channel 0 – SPORT0 Receive
0x0067 reserved
0x0068 II1 DMA Channel 1 – SPORT1 Receive (or Link Buffer 0)
0x0069 IM1 DMA Channel 1 – SPORT1 Receive (or Link Buffer 0)
0x006A C1 DMA Channel 1 – SPORT1 Receive (or Link Buffer 0)
0x006B CP1 DMA Channel 1 – SPORT1 Receive (or Link Buffer 0)
0x006C GP1 DMA Channel 1 – SPORT1 Receive (or Link Buffer 0)
0x006D DB1 DMA Channel 1 – SPORT1 Receive (or Link Buffer 0)
0x006E DA1 DMA Channel 1 – SPORT1 Receive (or Link Buffer 0)
0x006F reserved
0x0070 II2 DMA Channel 2 – SPORT0 Transmit
0x0071 IM2 DMA Channel 2 – SPORT0 Transmit
0x0072 C2 DMA Channel 2 – SPORT0 Transmit
0x0073 CP2 DMA Channel 2 – SPORT0 Transmit
0x0074 GP2 DMA Channel 2 – SPORT0 Transmit
0x0075 DB2 DMA Channel 2 – SPORT0 Transmit
0x0076 DA2 DMA Channel 2 – SPORT0 Transmit
0x0077 reserved
0x0078 II3 DMA Channel 3 – SPORT1 Transmit (or Link Buffer 1)
0x0079 IM3 DMA Channel 3 – SPORT1 Transmit (or Link Buffer 1)
0x007A C3 DMA Channel 3 – SPORT1 Transmit (or Link Buffer 1)
0x007B CP3 DMA Channel 3 – SPORT1 Transmit (or Link Buffer 1)
0x007C GP3 DMA Channel 3 – SPORT1 Transmit (or Link Buffer 1)
0x007D DB3 DMA Channel 3 – SPORT1 Transmit (or Link Buffer 1)
0x007E DA3 DMA Channel 3 – SPORT1 Transmit (or Link Buffer 1)
0x007F reserved
Table 10.9 SPORT DMA Parameter Registers

10.8.1.3 SPORT DMA Chaining

In chained DMA operations, the ADSP-2106x automatically sets up
another DMA transfer when the contents of the current buffer have
been transmitted (or received). The chain pointer register (CP) is used
to point to the next set of buffer parameters stored in memory. The
ADSP-2106x's DMA controller automatically downloads these buffer
parameters to set up the next DMA sequence. Refer to the DMA
chapter of this manual for details on how to set up chaining
parameters in memory.
www.BDTIC.com/ADI
Serial Ports 10
10 – 35