External Memory Interfacing - Analog Devices ADSP-2106x SHARC User Manual

5.4

EXTERNAL MEMORY INTERFACING

In addition to its on-chip SRAM, the ADSP-2106x provides addressing of
up to 4 gigawords of off-chip memory through its external port. This
external address space includes multiprocessor memory space, the on-chip
memory of all other ADSP-2106xs connected in a multiprocessor system,
as well as external memory space, the region for standard addressing of
off-chip memory.
Table 5.7 defines the ADSP-2106x pins used for interfacing to external
memory. Memory control signals allow direct connection to fast static
RAM devices. Memory-mapped peripherals and slower memories are
also supported, with a user-defined combination of programmable wait
states and hardware acknowledge signals. The suspend bus tristate pin
SBTS
( ) and page boundary pin (PAGE) can be used with DRAM
memory.
External memory can hold both instructions and data. The external
data bus (DATA ) must be 48 bits wide to transfer instructions
47-0
and/or 40-bit extended-precision floating-point data, or 32 bits wide to
transfer single-precision floating-point data. If external memory
contains only data or packed instructions that will be transferred by
DMA, the external data bus width can be either 16 or 32 bits. In this
type of system, the ADSP-2106x's on-chip I/O processor handles
unpacking operations on data coming into it and packing operations
on data going out. Figure 5.a shows how different data word sizes are
transferred over the external port.
DATA
47 40 32
16-Bit Packed
32-Bit Float or Fixed,
D31 - D0,
32-Bit Packed
40-Bit Extended Float
Instruction Fetch
Figure 5.a External Port Data Alignment
www.BDTIC.com/ADI
Memory
47-0
24 16 8
EPROM
Boot
5
0
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