Overview - Analog Devices ADSP-2106x SHARC User Manual

Host Interface 8
8.1

OVERVIEW

The ADSP-2106x's host interface allows easy connection to standard
microprocessor buses, both 16-bit and 32-bit, with little additional
hardware required. The ADSP-2106x accommodates either
synchronous or asynchronous data transfers, allowing the host to use a
different clock frequency. Asynchronous transfers at speeds up to the
full clock rate of the processor are supported. The host accesses the
ADSP-2106x through its external port, via the external bus (DATA
47-0
and ADDR ). The host interface is memory-mapped into the unified
31-0
address space of the ADSP-2106x. Figure 8.1 shows a block diagram of
the external port, I/O processor, and FIFO data buffers, illustrating the
on-chip data paths for host-driven transfers. The four external port
DMA channels are available for use by the host—DMA transfers of
code and data can be performed with low software overhead.
The host processor requests and controls the ADSP-2106x's external
HBR HBG
bus with the host bus request ( ), host bus grant ( ), and ready
(REDY) signals. Once it has gained control of the bus, the host can can
directly read and write the internal memory of the ADSP-2106x. It can
also read and write to any of the ADSP-2106x's IOP registers,
including the EPBx FIFO buffers. The host uses certain IOP registers to
control and configure the ADSP-2106x, SYSCON and SYSTAT for
example, and to set up DMA transfers. DMA transfers are controlled
by the ADSP-2106x's on-chip DMA controller once they have been set
up by the host (or by the ADSP-2106x core). In a multiprocessor
system, the host can access the internal memory and IOP registers of
every ADSP-2106x. Vector interrupts provide efficient execution of
host commands.
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