System Bus Interfacing - Analog Devices ADSP-2106x SHARC User Manual

8 Host Interface
write may complete before the direct write. Because of this, direct
writes performed just before vector interrupt writes (to VIRPT) may be
delayed until after the branch to the interrupt vector:
1. The host processor performs a direct write to the internal memory of
an ADSP-2106x.
2. The host processor writes to the VIRPT register of the ADSP-2106x
to initiate a vector interrupt. This causes the direct write to be
delayed.
4. The ADSP-2106x jumps to the vector interrupt service routine.
5. The direct write is completed after the interrupt service routine is
underway.
To prevent this from happening, the host should check that all direct
writes have completed before writing to the ADSP-2106x's VIRPT
register. This can be done by polling the ADSP-2106x's DWPD bit (in
SYSTAT) after performing a direct write, waiting for it to become
cleared, and then proceeding with the write to VIRPT.
8.8

SYSTEM BUS INTERFACING

An ADSP-2106x subsystem, consisting of several ADSP-2106xs with
local memory, may be viewed as one of several processing elements
connected together by a system bus. Examples of such systems are the
EISA bus, PCI bus, or even several ADSP-2106x subarrays. The
processing elements in such a system arbitrate for the system bus via
an arbitration unit. Each device on the bus that wishes to become a bus
master must be able to drive a bus request signal and respond to a bus
grant signal. The arbitration unit determines which request it will
grant in any given cycle.
8.8.1 Access To The ADSP-2106x Bus—Slave ADSP-2106x
Figure 8.7 shows an example of a basic interface to a system bus which
isolates the local ADSP-2106x bus from the system bus. When the
system is not accessing the ADSP-2106xs, the local bus supports
transfers between other local ADSP-2106xs and/or local external
memory or devices.
When the system wishes to access an ADSP-2106x, it executes a read or
write to the address range of the ADSP-2106x subsystem. The external
address comparator detects a local access and asserts
the appropriate
ADSP-2106x is ready to accept the data. The
system bus buffers. The buffers' direction for data is controlled by the
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CS
lines. The system bus is held off by REDY until the
HBR
and one of
HBG
signal enables the