Loading The Remaining Eprom Data - Analog Devices ADSP-2106x SHARC User Manual

BMS
selected by the pin; other memory select pins are disabled. The DMA
external count register (EC6) decrements after each EPROM transfer.
When EC6 reaches zero, the following wake-up sequence occurs:
1. The DMA transfers stop.
2. The External Port DMA Channel 6 interrupt (EP0I) is activated.
BMS
3. is deactivated and normal external memory selects are activated.
4. The ADSP-2106x vectors to the EP0I interrupt vector at 0x0002 0040.
At this point the ADSP-2106x has completed its booting mode and is
executing instructions normally. The first instruction at the EP0I interrupt
vector location, address 0x0002 0040, should be an RTI (Return From
Interrupt). This will return execution to the reset routine at location
0x0002 0005 where normal program execution can resume. After this has
occurred, your program can write a different service routine at the EP0I
vector location 0x0002 0040.
Remember that when using any of the power-up booting modes, location
0x0002 0004 should not contain a valid instruction since it is not executed
during the booting sequence. A NOP or IDLE instruction should be placed
at this location.

11.6.2.2 Loading The Remaining EPROM Data

The EPROM boot mode only loads 256 instructions during bootstrapping.
If your entire application must be loaded into internal memory from the
EPROM, the ADSP-2106x must gain access to the boot EPROM after
bootstrapping has completed. The BSO bit in the SYSCON register
provides this capability.
The BSO bit, when set, overrides the external memory selects and causes
BMS
the pin to assert (low) for an external port DMA transfer. Your
bootstrap program should first set the BSO bit in SYSCON and then set up
an external port DMA channel to read the rest of the EPROM's contents.
Any of the four external port DMA channels may be used:
Control
Channel# Register
DMA Channel 6 DMAC6
DMA Channel 7 DMAC7
DMA Channel 8 DMAC8
DMA Channel 9 DMAC9
When BSO=1, the PMODE packing mode bits in the DMAC6 control
register are ignored and 8-to-48 bit packing is forced for reads. (Note that
8-bit packing is only available during EPROM booting or on DMA reads
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System Design
Data
Buffer
EPB0 (Ext. Port DMA Buffer 0)
EPB1 (Ext. Port DMA Buffer 1)
EPB2 (Ext. Port DMA Buffer 2)
EPB3 (Ext. Port DMA Buffer 3)
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