Data Delays, Latencies, & Throughput - Analog Devices ADSP-2106x SHARC User Manual

11 System Design
To assure single-cycle, parallel accesses of two on-chip memory
locations, the following conditions must be met:
• The two addresses must be located in different memory blocks
(i.e. one in Block 0, one in Block 1).
• One address must be generated by DAG1 and the other by DAG2.
• The DAG1 address must not point to the same memory block that
instructions are being fetched from.
• The instruction should be of the form:
compute , Rx=DM(I0-I7,M0-M7), Ry=PM(I8 -I15,M8-M15);
(Note that reads and writes may be intermixed.)
11.8 DATA DELAYS, LATENCIES, & THROUGHPUT
Tables 11.5 and 11.6 specify data delays, latencies, and throughput for
the ADSP-2106x. Data delay and latency are defined as the number of
cycles (after the first cycle) required to complete the operation. Thus a
zero-wait-state memory has a data delay of zero, and a single-wait-
state memory has a data delay of one. Throughput is the maximum rate
at which the operation is performed.
Data delay and throughput are the same whether the access is from a
host processor or from another ADSP-2106x.
11.9 EXECUTION STALLS
The following events can cause execution stalls in the ADSP-2106x
core.
Program Sequencer Stalls
• 1 cycle on a program memory data access with instruction cache miss
• 2 cycles on non-delayed branches
• 2 cycles on normal interrupts
• 5 cycles on vector interrupt (VIRPT)
• 1-2 cycles on short loops w/small iterations
• n cycles on IDLE instruction
DAG Stalls
• 1 cycle hold on register conflict
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