Analog Devices ADSP-2106x SHARC User Manual page 689

Context switching
1-8, 1-9, 1-11, 2-12, 2-28, 4-3
Core priority access (CPA) ........................ 7-9
Core processor ............ 1-8, 1-11, 7-16, 7-17,
........................ 7-21, 8-13, E-2, E-36, G-1
Core processor access ................ 11-32, 11-46
Core processor buses ............................... 1-10
Core processor priority ........................... E-29
Count register (C) ............... 6-21, 6-24, 6-33,
.................................................. 6-35, 11-30
Counter-based loops .......... 3-15, 3-16, 3-17,
........................................ 3-19, 3-20, 11-40
CRBM bits (SYSTAT register) ...... 7-11, 7-19
Crossbar bus switch ................................... 1-1
Crosstalk ...................................... 11-24, 11-25
CS ... 8-8, 8-9, 8-16, 8-34, 11-33, 11-35, G-2
Current bus master .................................. E-30
Current loop count ..................................... 3-5
Current loop counter (CURLCNTR) ...... 3-5,
...................... 3-7, 3-15, 3-19, 3-20, A-36
D
DADDR ........................................................ 3-5
DAG register transfers ............................ 4-11
DAG register transfer restrictions .......... 4-12
DAG registers .................... 11-40, 11-41, A-7
DAG1 ... 5-3, 5-4, 5-5, 5-8, 5-9, 11-43, E-20
DAG1 bit-reversing .................................. 4-10
DAG1 registers ... 4-2, 4-3, 4-11, 4-12, A-48
DAG2 ....... 1-9, 3-4, 3-9, 3-38, 5-3, 5-4, 5-5,
........................ 5-8, 5-9, 11-43, E-20, G-3
DAG2 bit-reversing .................................. 4-10
DAG2 registers ... 4-2, 4-3, 4-11, 4-12, A-48
Damping resistance ................................ 11-22
Data address generators .................. 3-9, A-6
Data buffer ...................................... 6-23, 6-29
Data memory .......... 11-42, A-40, A-41, G-3
Data packing ............. 1-13, 1-15, 5-35, 6-14,
............ 6-22, 6-36, 8-5, 8-10, 8-19, 8-26,
............................... 9-9, 10-16, E-43, E-49
Data register file ......................................... 1-8
Data registers .................................... 2-6, 2-27
Data structures ............................................ 1-9
Data word width ...................................... E-27
DCPR bit (SYSCON register) .................. 6-26
Deadlock resolution ......................... 8-7, 8-13
Decode address ........................................... 3-5
def21060.h file ................................ 3-25, E-54
Delay ........................................................ 11-22
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Index
Delay lines ................................................... 1-9
Delayed branch (DB) ............ 3-9, 3-10, 3-11,
........................... 3-12, 3-24, 11-38, 11-40,
............................. A-5, A-28, A-30, A-34
Denormal operands ......................... 2-3, 2-16
Development tools ................................... 1-18
Digital filters ................. 1-9, 1-10, 5-4, 11-43
Direct addressing ................. 1-11, A-7, A-40
Direct branch ............................................... 3-9
Direct reads ............... 6-25, 11-46, E-26, G-2
Direct reads and writes ........................... 7-26
Direct write buffer .................................... 7-22
Direct write pending ............................... E-31
Direct writes ............ 6-25, 7-34, 8-33, 11-46,
..................................................... E-26, G-2
DM Address bus .............. 4-1, 4-2, 4-4, 5-36
DM bus .... 5-5, 5-8, 5-19, 7-21, 8-13, 11-42,
........... 11-43, 11-45, E-8, E-9, E-29, G-3
DM bus addresses ...................................... 5-9
DM Data bus ...... 2-27, 4-11, 5-6, 6-36, 8-18
DMA ................................................ 9-13, 9-16
DMA (two-dimensional) ........................... 6-7
DMA address generation . 6-22, 6-24, 11-45
DMA buffer ............................................. 11-45
DMA buffer registers ................................. E-8
DMA chaining .......... 6-10, 6-22, 6-25, 6-33,
................. 8-14, 10-15, 10-16, E-31, E-39
DMA chaining enable bit
(CHEN) .................................. 6-28, E-34
DMA channel 1 ......................................... 6-17
DMA channel 3 ......................................... 6-17
DMA channel 6 ..... 3-26, 6-17, 11-27, 11-30,
................................................. 11-32, 11-34
DMA channel 6 interrupt (EP0I) 11-31, 11-33
DMA channel 6-9 priority ....................... E-24
DMA channel 7 ......................................... 6-17
DMA channel parameter registers ......... 6-30
DMA channel prioritization ................... 6-48
DMA channels ........... 6-20, 6-21, 6-22, E-36
DMA controller ..... 1-12, 1-13, 11-27, 11-30,
.................................................... 11-31, G-1
DMA count register ............. 6-28, 6-33, 6-35
DMA cycle ................................................. 6-21
DMA enable ................................................ 9-7
DMA enable bit (DEN) .......... 6-6, 6-9, 6-35,
.................... 7-27, 8-19, E-34, E-41, E-49
DMA handshake ....... 5-41, 6-12, 6-43, 6-45,
.......................................... 6-48, 8-39, E-32
DMA interrupt priority ........................... 6-26
DMA interrupt vectors ............................ 6-33
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