Asynchronous Transfers - Analog Devices ADSP-2106x SHARC User Manual

8 Host Interface
• Synchronous accesses may not be used in systems with only one
ADSP-2106x (with ID
Once the host has finished its task, it can relinquish control of the bus
HBR
by deasserting
HBG
deasserting
assumes control of the bus and normal multiprocessor arbitration
resumes. The host should not deassert
its last data transfer with the ADSP-2106x.
8.2.2

Asynchronous Transfers

To initiate asynchronous transfers after acquiring control of the
ADSP-2106x's external bus, the host must assert the
ADSP-2106x it wants to access. This informs the ADSP-2106x that it
will be transferring data asynchronously with the host. The host must
then drive the address of the memory location or IOP register that it
wants to access. To simplify the hardware requirements for external
interface logic, only the address bits shown in Table 8.2 need to be
driven.
Address
Bits * Comments
ADDR Must be driven in all cases.
7-0
ADDR Must be driven only if the S field indicates an internal memory access.
16-8
ADDR S field**—Must be driven "00" for IOP register accesses, "01" for
18-17
internal memory accesses, or "1m" for short word accesses.
and either
ADDR M field**—Must be driven "000" to prevent other non-selected
21-19
ADSP-2106xs on the bus from thinking that a synchronous
multiprocessor memory space access is occurring.
or
ADDR E field**—one of the lines 31-22 driven as "1".
31-22
Table 8.2 Address Bits To Be Driven During Asynchronous Host Accesses
* Setup and hold times for these address lines are specified in the ADSP-2106x Data Sheet.
** For a complete description of these address fields, see "ADSP-2106x Memory Map"
in the Memory chapter of this manual.
Table 8.2 covers all cases, including multiprocessor systems, but fewer
address bits may need to be driven depending on the system. In a
single-ADSP-2106x system, the host need not drive the M address
field.
8 – 8
www.BDTIC.com/ADI
=000).
2-0
. The ADSP-2106x bus master responds by
. In the next cycle, the ADSP-2106x bus master again
HBR
until after it has completed
CS
pin of the