Idle & Idle16 - Analog Devices ADSP-2106x SHARC User Manual

Program Sequencing
The status stack flags are read-only. Writes to the STKY register have
no effect on these bits.
The overflow and full flags are provided for diagnostic aid only and
are not intended to allow recovery from overflow. Status stack or loop
stack overflow or PC stack full causes an interrupt.
The empty flags facilitate stack saves to memory. You monitor the
empty flag when saving a stack to memory to know when all values
have been transferred. The empty flags do not cause interrupts because
an empty stack is an acceptable condition.
3.9 IDLE & IDLE16
IDLE and IDLE16 are special instructions that halt the ADSP-2106x
core processor in a low-power state until an external interrupt (
timer interrupt, DMA interrupt, or VIRPT vector interrupt occurs.
When the processor executes an IDLE instruction, it fetches one more
instruction at the current fetch address and then suspends operation.
The ADSP-2106x's I/O processor is unaffected by the IDLE
instruction—any DMA transfers to or from internal memory will
continue uninterrupted.
The processor's internal clock continues to run during IDLE, as well as
the timer (if it is enabled). When an external interrupt (
interrupt, DMA interrupt, or VIRPT vector interrupt occurs, the
processor responds normally. After two cycles needed to fetch and
decode the first instruction of the interrupt service routine, the
processor continues executing instructions normally.
On the ADSP-21061 only, the IDLE16 instruction executes a NOP and puts
the processor in a low power state. IDLE16 is a lower power version of the
IDLE instruction. This instruction halts the processor like the IDLE
instruction; in this case, the internal clock runs at 1/16th the rate of
CLKIN. The ADSP-21061's I/O processor continues to function, but all
operations occur at 1/16th the rate. All internal memory transfers require
an extra 15 cycles. The serial clocks and frame syncs (if being sourced by
the ADSP-21061) are divided down by a factor of 16 during IDLE16.
Similarly, all Host accesses take 16 times longer to complete. The
processor remains in the low power state until an interrupt occurs.
After returning from the interrupt, execution continues at the
instruction following the IDLE or IDLE16 instruction.
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IRQ
),
2-0
IRQ
), timer
2-0
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