Transferring Data Between Sports And Memory - Analog Devices ADSP-2106x SHARC User Manual

Processor B can check for this key word as follows:
1. Set the KEYWD register to "START TRANSMIT TO B"
2. Clear bits 31:16 of the KEYMASK register to 0 and set the other
bits to 1
This step enables comparison only for bits 31:16. So, assume that
the code for "START TRANSMIT TO B" only uses bits 31:16 and
bits 15:0 indicate the source of the transmission and the data
channels.
3. Set bits 15 and 20 of the SRCTL register to 1
This step enables the SPORT to generate an interrupt or DMA
request only if the incoming data matches the KEYWD.
4. Set bits 0 through 3 of the Transmit Compand Channel Selector
register to 1 and clear the remaining bits to 0
This step enables comparison only on channels 0 through 3.
Until it receives the "START TRANSMIT TO B" keyword, processor B
ignores all transmissions that it receives. When processor A wants to
send data to B, it sends the "START TRANSMIT TO B" keyword on
channel 0. When receive comparison on processor B recognizes the
"START TRANSMIT TO B" keyword, the SPORT interrupts processor
B. Then, processor B analyzes the remaining 16-bits, determining that
the source is processor A and the data is on channels 4 through 10.
Because processor A is using channels 4 through 10 to transmit data,
processor B enables receive channels 4 through 10 and sends a
"READY TO RECEIVE DATA" message to processor A, using channel
1. After processor A receives this message, it sends the data on
channels 4 through 10. If the transfer protocol uses a fixed number of
bytes in each message, processor B could send back a checksum
message to processor A after receiving A's message, confirming that
the data transferred accurately.
10.8

TRANSFERRING DATA BETWEEN SPORTS AND MEMORY

Transmit and receive data can be transferred between the ADSP-2106x
serial ports and on-chip memory in one of two ways, with single-word
transfers or with DMA block transfers. Both methods are interrupt-
driven, using the same internally generated interrupts.
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Serial Ports 10
10 – 31