Analog Devices ADSP-2106x SHARC User Manual page 682

Errata and Corrections
Chapter: 3 Page: 24
Revision Needed:
In paragraph 3.6.2 at the bottom of the page, second sentence, the seg-
ment "eight memory locations" shou ld be replaced with "four memory
locations."
Chapter: 3 Page: 41
Revision Needed:
Add the following paragraph and note to the end of section 3.10.3 Cache
Disable & Cache Freeze:
The CADIS bit directs the sequencer to disable the cache (if 1) or enable
the cache (if 0). Disabling the cache does not mark the current content of
the cache as invalid. When the cache is enabled again, the existing content
is used again. To clear the cache use the FLUSH CACHE instruction.
Note: If self-modifying code (for example, software loader kernel) or soft-
ware overlays are used, execute a FLUSH CACHE instruction followed by
a NOP before executing the new code. Otherwise, old content from the
cache could still be used, although the code has changed.
Chapter: 7 Page: 31
Revision Needed:
A NOP instruction should be inserted as follows:
BIT SET MODE2 BUSLK;
NOP;
/* NOP accommodates one cycle effect latency when writing to
Mode2 */
IF NOT BM JUMP (PC,0);
H-6
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