Program Sequencer Registers & System Registers - Analog Devices ADSP-2106x SHARC User Manual

Program Sequencing
3.1.2.1 Program Sequencer Registers & System Registers
Table 3.1 lists the registers located in the program sequencer. The
functions of these registers are described in subsequent sections of this
chapter. All registers in the program sequencer are universal registers and
are thus accessible to other universal registers as well as to data memory.
All registers and the tops of stacks are readable; all registers except the
fetch address, decode address and PC are writeable. The PC stack can be
pushed and popped by writing the PC stack pointer, which is readable
and writeable. The loop address stack and status stack are pushed and
popped by explicit instructions.
The System Register Bit Manipulation instruction can be used to set, clear,
toggle or test specific bits in the system registers. This instruction is
described in Appendix A, Group IV–Miscellaneous Instructions.
Due to pipelining, writes to some of these registers do not take effect on
the next cycle; for example, if you write the MODE1 register to enable
ALU saturation mode, the change will not occur until two cycles after the
write. Also, some registers are not updated on the cycle immediately
following a write; it takes an extra cycle before a read of the register yields
the new value. Table 3.1 summarizes the number of extra cycles for a write
to take effect (effect latency) and for a new value to appear in the register
(read latency). A "0" indicates that the write takes effect or appears in the
register on the next cycle after the write instruction is executed. A "1"
indicates one extra cycle.
Program Sequencer
Registers Contents
FADDR* fetch address
DADDR* decode address
PC* execute address
PCSTK top of PC stack
PCSTKP PC stack pointer
LADDR top of loop address stack
CURLCNTR top of loop count stack (current loop count)
LCNTR loop count for next DO UNTIL loop
System Registers
MODE1 mode control bits
MODE2 mode control bits
IRPTL interrupt latch
IMASK interrupt mask
IMASKP interrupt mask pointer (for nesting)
ASTAT arithmetic status flags
STKY sticky status flags
USTAT1 user-defined status flags
USTAT2 user-defined status flags
Table 3.1 Program Sequencer Registers & System Registers
* read-only
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Read Effect
Bits Latency Latency
24 – –
24 – –
24 – –
24 0 0
5 1 1
32 0 0
32 0 0
32 0 0
32 0 1
32 0 1
32 0 1
32 0 1
32 1 1
32 0 1
32 0 1
32 0 0
32 0 0
3 – 5