E.3.2 Iop Register Access Restrictions - Analog Devices ADSP-2106x SHARC User Manual

E Control/Status Registers
E.3.2 IOP Register Access Restrictions
Because the IOP registers are memory-mapped they cannot be written
with data coming directly from memory. They must instead be written
from (or read into) ADSP-2106x core registers, usually one of the
general-purpose registers of the register file (R15–R0). The IOP
registers can also be written or read by external devices, usually other
ADSP-2106xs and/or a host processor.
IOP registers other than the DMA buffers cannot be the target of DMA
transfers. During DMA transfers the DMA buffer registers are written
and read to internal memory over the I/O data bus—these transfers
are directly controlled by the ADSP-2106x's DMA controller, however,
not with addresses generated over the I/O address bus. The DMA
buffer registers on the ADSP-21060 and ADSP-21062 include EPB0–
EPB3 (external port data buffers), LBUF0–LBUF5 (link port data
buffers), and TX0, RX0, TX1, and RX1 (serial port data buffers). On the
ADSP-21061, the DMA buffer registers include EBP0, EBP1, TX0, RX0,
TX1, and RX1.
E.3.3 IOP Register Group Access Contention
The ADSP-2106x has four separate on-chip buses that can
independently access the memory-mapped IOP registers: the PM bus,
DM bus, I/O bus, and external port bus. The external port bus
connects the off-chip DATA
connects the external port's data buffers to memory and to the on-chip
I/O processor. The I/O bus carries data being transferred to and from
the DMA buffer IOP registers.
Any of these buses can attempt to read or write an IOP register at any
time. Access contention occurs when more than one of the buses
attempts to access the same group of IOP registers (see Table E.7). One
exception to this access contention rule exists: the I/O bus and external
port bus can simultaneously access the DB (DMA buffer) group of
registers, allowing DMA transfers to internal memory at full speed.
IOP register group access conflicts are resolved on a fixed priority
basis. External port to IOP register accesses occur first, then
PM and/or DM bus, then I/O bus:
External port
PM-DM bus IOP register accesses
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bus to all on-chip buses. The I/O bus
47-0
IOP register accesses 1st priority
2nd priority