Analog Devices ADSP-2106x SHARC User Manual page 335

If the master wishes to give up the token, he may send back a user-
defined token release word and thereafter clear his token flag.
Simultaneously, the slave examines the data sent back and if it is the
token release word, the slave will set his token, and can thereafter
transmit. If the received data is not the token release word, then the
slave must assume the master was beginning a new transmission.
Through software protocol, the master can also ask to receive data by
sending the token release word without the LxACK (data request)
going low first.
An example of software protocol for token passing through the link
ports is included at the end of this chapter. Figure 9.7 shows a flow
chart of the example code and the following is a description of the
process:
The example code is to be loaded on both the original master and the
original slave. The code is ID intelligent for multiprocessor systems:
ID1 is the original master (transmitter) and ID2 is original slave
(receiver). The master transmits a buffer via DMA through LPORT0
using LBUF3 and the slave receives through LPORT0 using LBUF2.
The slave then requests the token by generating an LSRQ interrupt in
the disabled link port of the master (LPORT0). The master responds by
sending the token release word and waiting to see if it is accepted. The
slave checks to see that it is the token release word and will accept the
token by emptying the master's link buffer FIFO within a
predetermined amount of time. If the token is accepted the slave will
become the master and transmit a buffer of data to the new slave. If the
token is rejected, the master will transmit a second buffer. When
complete, the original master will finish by setting up LBUF2 to receive
without DMA, and the original slave will set up LBUF3 to transmit
without DMA.
The following is a list of the major areas of concern when
implementing a software protocol scheme for token passing:
• Ensure that both link buffers are not enabled to transmit at the same
time. In the event that this is allowed, data may be transmitted and lost
due to the fact that neither link port will be driving LxACK. In the
example provided at the end of the chapter, the LSRQ register status
bits are polled to ensure that the master becomes the slave before the
slave becomes the master, thus avoiding the two transmitter conflict.
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Link Ports 9
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