Single-Word Transfers - Analog Devices ADSP-2106x SHARC User Manual

10 Serial Ports
DMA chaining occurs independently for the transmit and receive
channels of each serial port. Each SPORT DMA channel has a chaining
enable bit (SCHEN) in the STCTLx and SRCTLx control registers. This
bit must be set to 1 to enable chaining. Writing all zeros to the address
field of the chain pointer register (CP) also disables chaining.
10.8.2

Single-Word Transfers

Individual data words may also be transmitted and received by the
serial ports, with interrupts occurring as each 32-bit word is
transmitted or received. When a serial port is enabled and DMA is
disabled (in the STCTLx or SRCTLx control registers), the SPORT
DMA interrupts will be generated in this way—whenever a complete
32-bit word has been received in the RX buffer, or whenever the TX
buffer is not full. Single-word interrupts can be used to implement
interrupt-driven I/O on the serial ports.
Whenever the ADSP-2106x core's program reads a word from a serial
port's RX buffer or writes a word to its TX buffer, the buffer's
full/empty status should first be checked in order to avoid hanging the
ADSP-2106x core. (This can also happen to an external device, for
example a host processor, when it is reading or writing a serial port
buffer.) The full/empty status can be read in the RXS bits of the SRCTLx
register or the TXS bits of the STCTLx register. Reading from an empty
RX buffer or writing to a full TX buffer causes the ADSP-2106x (or
external device) to hang, waiting for the status to change. To prevent
this hang condition from occurring, the BHD (Buffer Hang Disable) bit
should be set in the SYSCON register.
Multiple interrupts can occur if both SPORTs transmit or receive data
in the same cycle. Any interrupt can be masked out in the IMASK
register; if the interrupt is later enabled in IMASK, the corresponding
interrupt latch bit in IRPTL must be cleared in case the interrupt has
occurred in the meantime.
When serial port data packing is enabled (PACK=1 in the STCTLx or
SRCTLx control registers), the transmit and receive interrupts are
generated for the 32-bit packed words, not for each 16-bit word.
10.9 SPORT LOOPBACK
When the SPL bit (SPORT loopback) is set in the SRCTLx receive
control register, the serial port is configured in an internal loopback
connection. The loopback configuration allows the serial ports to be
tested internally.
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