Analog Devices ADSP-2106x SHARC User Manual page 147

When an address is applied to memory for a read or write, the
particular columns selected depends upon the word width of the
access. For 48-bit words, the 16-bit columns are selected in groups of
three. In a memory block consisting entirely of 48-bit instruction
words,
16 columns ÷ 3 columns per group = 5 groups
there are 5 groups to select from and the 16th column is unused. Thus,
an ADSP-21060 2-Mbit memory block that consists entirely of 48-bit
words provides
8K × 5 groups = 40K words
of instruction storage. For 32-bit data words, the columns are selected
in groups of two. In a memory block consisting entirely of 32-bit
words,
16 columns ÷ 2 columns per group = 8 groups
there are 8 words to select from with no columns unused. Thus, an
ADSP-21060 2-Mbit memory block that consists entirely of 32-bit
words provides
8K × 8 groups = 64K words
of data storage.
Because the memory on the ADSP-21061 is arranged in eight 16-bit
columns, a similar set of calculations for this processor yields the
following:
4K × 2 groups = 8K words (of instruction storage)
4K × 4 groups = 16K words (of data storage)
Figure 5.8 shows the ordering of 16-bit words within 48-bit words
and 32-bit words, and also shows initial addresses for each column of
ADSP-21060 memory. Figure 5.9a shows the same information for the
ADSP-21062, and Figure 5.9b shows this information for the ADSP-
21061.
www.BDTIC.com/ADI
Memory 5
5 – 21