Analog Devices ADSP-2106x SHARC User Manual page 327

DMA Channels 1 and 3 are shared by link buffers 0 and 1, respectively,
and by SPORT1. This has several functional implications:
• If the SPORT1 receive DMA enable bit or chaining enable bit is set, then
SPORT1 receive is assigned DMA channel 1.
• If the LBUF0 DMA enable bit is set, then link buffer 0 is assigned this
DMA channel.
• If both enables are set, the SPORT is selected.
• If neither the SPORT DMA enable or LBUF0 DMA enable is set, then
interrupts from both buffers are ORed.
SPORT1 transmit and LBUF1 are shared and selected in the same way.
DMA Channel 6 is shared by the external port buffer EPB0 and link
buffer 4 (LBUF4). Functional implications include:
• If the EPB0 DMA enable bit or chaining enable bit is set, then EPB0 is
assigned DMA channel 6.
• If the LBUF4 DMA enable bit is set, then link buffer 4 is assigned this
DMA channel.
• If both enables are set, EPB0 is selected.
• If neither the external port DMA enable or LBUF4 DMA enable is set,
then interrupts from both buffers are ORed.
EPB1 and LBUF5 share DMA channel 7 and are selected in the same
way.
A maskable interrupt is generated when the DMA block transfer has
completed. A more complete discussion on interrupts can be found in
the "Link Port Interrupts" section of this chapter.
If DMA is disabled for a buffer, then the buffer may be read or written
by the core processor as a memory-mapped location. A maskable
interrupt is generated while DMA is disabled and the receive buffer is
not empty or if the transmit buffer is not full.
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Link Ports 9
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