Figure 6.11 Example Dma Hardware Interface - Analog Devices ADSP-2106x SHARC User Manual

6 DMA
ADSP-2106x
BR BR 2 2 ADDR ADDR 31-0
31-0
5
BR BR 1 1 BR BR 3-6
DATA
, DATA 47-0
3-6
47-0
3
ID ID 2-0
010
2-0
DMAR1 DMAR1
DMAG1 DMAG1
DMAR2 DMAR2
DMAG2 DMAG2
HBR HBR
HBG HBG
RD
RD
WR WR
ACK
MS MS 3-0
3-0
ADSP-2106x
ADD
ADDR R 31-0
BR BR 1 1
31-0
5
DATA DATA 47-0
BR BR 2-6
47-0
2-6
3
ID ID 2-0
001
DMAR1 DMAR1
2-0
DMAG1 DMAG1
DMAR2 DMAR2
DMAG2 DMAG2
HBR HBR
HBG HBG
RD RD
WR WR
ACK
MS 3-0 MS
3-0

Figure 6.11 Example DMA Hardware Interface

Notes:
DMARx DMAGx
– Because and
have DMA enabled at a time.
DMAGx
– is only driven by the ADSP-2106x bus master.
– The DMA Write Grant signal can be the combination of
if paced master mode is used.
– The DMA Read Grant signal can be the combination of
if paced master mode is used.
– DMA transfers may be to either ADSP-2106x or to external memory
(in external handshake mode).
6 – 50
www.BDTIC.com/ADI
16, 32, or 48
16, 32, or 48
OE OE
WE WE
ACK
EXTERNAL
CS CS
MEMORY
ADDR
ADDR
DATA DATA
are tied together, only one of the ADSP-2106xs may
RD
and
WR
and
Latch
D Q DMA Data Bus
OE OE
DMA Read Request
DMA Read Grant
Latch
Q D DMA Data Bus
OE OE
DMA Write Request
DMA Write Grant
MSx DMAG2
instead of
MSx DMAG1
instead of