Deadlock Resolution - Analog Devices ADSP-2106x SHARC User Manual

8 Host Interface

8.8.2.2 Deadlock Resolution

In the rare case where both the ADSP-2106x subsystem and the system
are trying to access each other's bus in the same cycle, a deadlock may
occur in which neither access can complete; ACK stays deasserted.
Normally the master ADSP-2106x will respond to an
HBG
asserting
ADSP-2106x is accessing the system bus at the same time, however,
HBG
will not be asserted because this current access cannot
complete—this results in a deadlock in which neither access can
complete. The deadlock may be broken by asserting the
one or more cycles once the deadlock is detected (i.e. when the system
bus to local bus buffer is enabled from both sides).
Bus Tristate pin of the ADSP-2106x.
The combination of
slave mode, just like a normal
ADSP-2106x core's external access. This allows the system access to the
local bus to proceed, once the ADSP-2106x asserts
combination of
deadlock caused by an ADSP-2106x access to the system bus. It should
not be used when there is a local bus transfer because the
will be asserted twice, once before the SBTS is asserted and once after
the access resumes. For SHARC-to-SHARC transfers on the local bus,
this will violate the slave timing requirements.
The following sequence of actions allows the host processor to suspend
an ongoing ADSP-2106x access and gain access to its internal
resources, provided that: 1) the access originates from the
ADSP-2106x's core, not the DMA controller, 2) a DRAM PAGE miss is
not detected for that memory access, and 3) bus lock is not enabled.
HBR
1. After
SBTS
If is asserted one or more cycles after
is guaranteed to be asserted in the next cycle.
deasserted before
2. The host drives both
(within the setup time specified in the data sheet) after
asserted. The host may then perform as many accesses as desired.
3. The host has full control of the bus and may access any of the
ADSP-2106xs or peripherals on the bus.
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after the completion of the current access. If the
SBTS HBR
and puts the master ADSP-2106x into
HBR
assertion, and suspends the
HBR SBTS
and should only be applied when there is a
is asserted, the host asserts
HBR
is deasserted.
RD WR
and strobes to their correct value
HBR
request by
SBTS
input for
SBTS
is the Suspend
HBG
. The
WR
signal
SBTS
for one or more cycles.
HBR HBG
is recognized,
SBTS
should be
HBG
is