Analog Devices ADSP-2106x SHARC User Manual page 656

E Control/Status Registers
LSRQ
31 30 29 28
0
0x00C9
L5RRQ
Link Port 5 Receive Request
L5TRQ
Link Port 5 Transmit Request
L4RRQ
Link Port 4 Receive Request
L4TRQ
Link Port 4 Transmit Request
L3RRQ
Link Port 3 Receive Request
L3TRQ
Link Port 3 Transmit Request
15 14 13 12
0
L5RM
Link Port 5 Receive Mask
L5TM
Link Port 5 Transmit Mask
L4RM
Link Port 4 Receive Mask
L4TM
Link Port 4 Transmit Mask
L3RM
Link Port 3 Receive Mask
L3TM
Link Port 3 Transmit Mask
All control and status bits are active high unless otherwise
noted. Default bit values after reset are shown; if no value
is shown, the bit is undefined at reset or depends upon
processor inputs. Reserved bits are shown with a gray
background. Reserved bits should always be written with zeros.
E – 48
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27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Request Bits are Read-Only Status
11 10 9 8 7
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
L0TRQ
Link Port 0 Transmit Request
L0RRQ
Link Port 0 Receive Request
L1TRQ
Link Port 1 Transmit Request
L1RRQ
Link Port 1 Receive Request
L2TRQ
Link Port 2 Transmit Request
L2RRQ
Link Port 2 Receive Request
6 5 4 3 2 1 0
0 0 0 0 0 0 0
L0TM
Link Port 0 Transmit Mask
L0RM
Link Port 0 Receive Mask
L1TM
Link Port 1 Transmit Mask
L1RM
Link Port 1 Receive Mask
L2TM
Link Port 2 Transmit Mask
L2RM
Link Port 2 Receive Mask