Acquiring The Bus - Analog Devices ADSP-2106x SHARC User Manual

8 Host Interface
8.2.1

Acquiring The Bus

For a host processor to gain access to the ADSP-2106x, it must first
HBR
assert , the host bus request signal.
multiprocessor bus requests, and when asserted will cause the current
ADSP-2106x master to give up the bus to the host as soon as it has
finished the current bus cycle.
The current ADSP-2106x bus master signals that it is transferring
ownership of the bus by asserting
bus operation has completed. The cycle in which control of the bus is
transferred is called a host transition cycle (HTC).
Figure 8.2 shows the timing for bus acquisition by the host.
asserted during the ADSP-2106x's bus transition cycle (BTC) and
remains asserted until
transition cycle (BTC) shown in Figure 8.2 is the same as that of a
SHARC-to-SHARC multiprocessor BTC, as described in Chapter 7,
HBG
Multiprocessing.
arbitration during the time that the host owns the bus. (
also be used to enable the host's signal buffers, as shown in Figure 8.8
at the end of this chapter.) While
will continue to assert and deassert their
operation, but no BTCs will occur. The current ADSP-2106x bus master
BR
will keep its x asserted throughout the entire time the host controls
the bus.
Once the host has gained control of the bus, it can choose to perform
either synchronous or asynchronous transfers with the ADSP-2106x(s).
To initiate asynchronous transfers, the host asserts (low) the
the ADSP-2106x that it intends to access and performs the read or
CS
write. ( is ignored when
synchronous transfers, the host keeps all ADSP-2106x
deasserted (high) and reads or writes to the ADSP-2106xs'
multiprocessor memory space (just as one ADSP-2106x reads or writes to
another ADSP-2106x).
The host is responsible for driving the following signals during the
HTC in which it gains control of the bus: ADDR
PAGE. See Figure 8.3. These signals must also continue to be driven for
the entire time the host has the bus. In addition, the
DMAG1 DMAG2
, and
down—the ADSP-2106x bus master tristates these lines to allow the
host the possibility of using them.
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HBR
has priority over all
HBG
(low) as soon as the current
HBR
is deasserted by the host. (The bus
freezes ADSP-2106x multiprocessor bus
HBG
is asserted, the ADSP-2106xs
BR
x lines as in normal
HBG
is not asserted.) To initiate
lines must be driven or weakly pulled up or
BR
x
HBG
is
HBG
should
CS
pin of
CS
pins
RD WR SW
, , , , and
31-0
MS
, ADRCLK,
3-0