Table of Contents
Advertisement
9 Link Ports
9.4.1
Core Processor Access To Link Buffers
In applications where the latency of link port DMA transfers to and
from internal memory is too long, or where a process is continuous
and has no block boundaries, the ADSP-2106x processor core may read
or write link buffers directly using the full/empty status bit of the link
buffer to automatically pace the operation. The full or empty status of a
particular LBUFx buffer can be determined by reading the LCOM
control/status register. DMA should be disabled (i.e. the LxDEN bit
should be cleared) when using this capability. A programming
example of core-driven transfers is shown at the end of this chapter.
If a read is attempted from an empty receive buffer, the core will hang
until the link port completes transmission of a word. Similarly, if a
write is attempted to a full transmit buffer, the core will hang until the
external device accepts the complete word. Up to four words (2 in the
receiver and 2 in the transmitter) may be sent without a hang before
the receiver core must read a link buffer register. To prevent this type
of hang condition from occurring, the BHD (Buffer Hang Disable) bit
can be set in the SYSCON register.
9.4.2
Host Processor Access To Link Buffers
The link buffers can also be accessed by the external host processor,
using direct reads and writes. When the host reads or writes to these
buffers, the word width is determined only by the host packing mode,
as selected by the HPM bits in the SYSCON register, and not by the
LEXT bit in LCTL.
9.5
LINK PORT DMA CHANNELS
Link buffers 0-5 are supported by DMA channels 1, 3, 4, 5, 6, and 7
respectively. Some DMA channels are dedicated and others are shared:
• DMA channel 1 is shared by SPORT1 receive and link buffer 0 (LBUF0).
• DMA channel 3 is shared by SPORT1 transmit and link buffer 1 (LBUF1).
• DMA channel 4 is dedicated to link buffer 2 (LBUF2).
• DMA channel 5 is dedicated to link buffer 3 (LBUF3).
• DMA channel 6 is shared by ext. port buffer 0 (EPB0) and link buffer 4.
• DMA channel 7 is shared by ext. port buffer 1 (EPB1) and link buffer 5.
9 – 16
www.BDTIC.com/ADI
Advertisement
Table of Contents
