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The MASTER, HSHAKE, and EXTERN bits configure the DMA mode in the
following manner:
M H E
DMA Mode of Operation
0
0
0
Slave Mode. The DMA request is generated whenever the receive
buffer is not empty or the transmit buffer is not full.
0
0
1
Reserved
0
1
0
Handshake Mode. (For the ADSP-21060 and ADSP-21062,
applies to EPB1, EPB2 buffers, channels 7, 8 only. For the ADSP-
21061, applies to EPB0, EPB1 buffers, channels 6, 7 only.) The
DMA request is generated when the
transfer occurs when
0
1
1
External Handshake Mode. (For the ADSP-21060 and ADSP-
21062, applies to EPB1, EPB2 buffers, channels 7, 8 only. For the
ADSP-21061, applies to EPB0, EPB1 buffers, channels 6, 7 only.)
Identical to Handshake Mode, but with data transferred between
external memory and an external device.
1
0
0
Master Mode. The DMA controller will attempt a transfer
whenever the receive buffer is not empty or the transmit buffer is
not full and the DMA counter is non-zero.
kept high (inactive) if channel 7 is in master mode, and
should be kept high if channel 8 is in master mode on the ADSP-
21060 or ADSP-21062.
in master mode on the ADSP-21061.
1
0
1
Reserved
1
1
0
Paced Master Mode. (For the ADSP-21060 and ADSP-21062,
applies to EPB1, EPB2 buffers, channels 7, 8 only. For the ADSP-
21061, applies to EPB0, EPB1 buffers, channels 6, 7 only.) In this
mode the transfers are paced by the
request is generated when
operate in the same way as in handshake mode. The bus transfer
RD
occurs when
normal master mode. No external gates are required to OR the
RD
DMAGx
-
and
access to be zero-waitstate with no idle states. Waitstates and
acknowledge (ACK) apply to Paced Master Mode transfers; see
Section 5.4.4, "Wait States & Acknowledge" in Chapter 5,
Memory.
1
1
1
Reserved
If data is to be read from the ADSP-2106x (i.e. TRAN=1), the EPBx buffer
1.
will be filled as soon as the DEN enable bit is set to 1.
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DMARx
DMAGx
1
is asserted.
DMAR1
1
DMAR2
should be kept high if channel 6 is
DMARx
signal—the DMA
DMARx
is asserted.
WR
or
is asserted. The address is driven as in
WR
DMAGx
-
pairs, thus allowing the buffer
DMA
6
1
line is asserted. The
should be
DMAR2
DMARx
requests
6 – 13
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