Analog Devices ADSP-2106x SHARC User Manual page 163

Pin Type Function
WR
I/O/T Memory Write Strobe. This pin is asserted (low) when the ADSP-
2106x writes to external memory devices or to the internal memory
of other ADSP-2106xs. External devices must assert
the ADSP-2106x's internal memory. In a multiprocessing system
WR
is output by the bus master and is input by all other ADSP-
2106xs.
PAGE O/T DRAM Page Boundary. The ADSP-2106x asserts this pin to signal
that an external DRAM page boundary has been crossed. DRAM
page size must be defined in the
register (WAIT). DRAM can only be implemented in external
memory Bank 0; the PAGE signal can only be activated for Bank 0
accesses. In a multiprocessing system PAGE is output by the bus
master.
SW
I/O/T Synchronous Write Select. This signal is used to interface the
ADSP-2106x to synchronous memory devices (including other
ADSP-2106xs). The ADSP-2106x asserts
early indication of an impending write cycle, which can be aborted
WR
if
a multiprocessing system,
input by all other ADSP-2106xs to determine if the multiprocessor
memory access is a read or write.
the address output. A host processor using synchronous writes
must assert this pin when writing to the ADSP-2106x(s).
ACK I/O/S Memory Acknowledge. External devices can deassert ACK (low)
to add wait states to an external memory access. ACK is used by I/
O devices, memory controllers, or other peripherals to hold off
completion of an external memory access. The ADSP-2106x
deasserts ACK as an output to add wait states to a synchronous
access of its internal memory. In a multiprocessing system, a slave
ADSP-2106x deasserts the bus master's ACK input to add wait
state(s) to an access of its internal memory. The bus master has a
keeper latch on its ACK pin that maintains the input at the level it
was last driven to.
I=Input S=Synchronous
O=Output A=Asynchronous
SBTS HBR
T=Tristate (when or
Table 5.7 External Memory Interface Signals
www.BDTIC.com/ADI
is not later asserted (e.g. in a conditional write instruction). In
SW
is output by the bus master and is
SW
(o/d)=Open Drain
(a/d)=Active Drive
is asserted, or when the ADSP-2106x is a bus slave)
Memory
WR
to write to
ADSP-2106x's memory control
SW
(low) to provide an
is asserted at the same time as
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