Overview - Analog Devices ADSP-2106x SHARC User Manual

9.1

OVERVIEW

The ADSP-2106x SHARC provides additional I/O capability through
six dedicated 4-bit link ports. Each link port consists of four
bidirectional data lines, a bidirectional clock line, and a bidirectional
acknowledge line. The link ports can be clocked twice per processor
clock cycle, allowing each port to transfer up to 8 bits of data per cycle.
Link port I/O allows a variety of interconnection schemes to I/O
peripheral devices as well as coprocessing and multiprocessing
schemes. Using link port I/O, it is also possible to configure
multidimensional, multiprocessor arrays.
Note that the ADSP-21061 processor does not have link ports; the
discussion in this chapter does not apply to the ADSP-21061.
Link port features and functions include:
• Link ports can operate independently and simultaneously.
• Link port data is packed into 32-bit or 48-bit words, and can be directly
read by the ADSP-2106x core processor or DMA-transferred to on-chip
memory.
• Link port data can also be accessed by the external host processor, using
direct reads and writes.
• Double-buffered transmit and receive data registers.
• Clock/acknowledge handshaking controls link port transfers which are
programmable as either transmit or receive with each link port
supported by a separate DMA channel.
• Link ports provide high-speed, point-to-point data transfers to other
ADSP-2106x processors. This allows a variety of interconnection
schemes between multiple ADSP-2106x processors and external
devices, including 1-, 2- and 3-dimensional arrays.
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Link Ports 9
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