External Memory Space - Analog Devices ADSP-2106x SHARC User Manual

(M=ID =000). Addresses with M=ID
2-0
single-processor systems.
If the ADSP-2106x attempts to access an invalid address in
multiprocessor memory space, data written will be ignored and reads
will return invalid data.
For additional information about multiprocessor memory accesses, see
"Direct Reads & Writes" and "Data Transfers Through The EPBx
Buffers" in the Multiprocessing chapter of this manual.
5.2.6

External Memory Space

External memory can be accessed over the ADSP-2106x's DM bus,
PM bus, and EP bus, all via the external port. The processor's DAG1,
program sequencer (and DAG2), and IOP control these respective
buses.
32-bit addresses are generated by DAG1 and the IOP over the DM address
bus and I/O address bus, allowing addressing of the complete 4-gigaword
memory map. The program sequencer and DAG2 generate 24-bit
addresses over the PM address bus, limiting addressing to the low
12 megawords (0x0040 0000 to 0x00FF FFFF).
5.2.7 Memory Space Access Restrictions
The ADSP-2106x's three internal buses, PM, DM, and I/O, can be used
to access the processor's memory map according to the following rules:
• The DM bus can access all memory spaces.
• The PM bus can access only Internal Memory Space and the lowest
12 megawords of External Memory Space.
• The I/O bus can access all memory spaces except for the memory-
mapped IOP registers (in Internal Memory Space).
Note that in silicon revision 1.0 and earlier pre-modify addressing
operations must not change the memory space of the address; for
example, pre-modification of an address in Internal Memory Space
should not generate an address in External Memory Space. The one
exception to this rule is: an indirect JUMP or CALL instruction with
pre-modify addressing can jump from internal memory to external
memory. Silicon revisions 2.x and later do not have this pre-modify
limitation.
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Memory
=000 are only allowed in
2-0
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