Multiprocessor Memory - Analog Devices ADSP-2106x SHARC User Manual

5 Memory
3. The ADSP-2106x checks whether wait states are needed. If so, the
memory select and write strobe remain active for additional cycle(s).
Wait states are determined by the state of the external acknowledge
signal, the internally programmed wait state count, or a combination
of the two.
4. The ADSP-2106x deasserts the write strobe near the end of the cycle.
5. The ADSP-2106x tristates its data outputs.
6. If initiating another memory access, the ADSP-2106x drives the
address and memory select for the next cycle.
Note that if a memory write is part of a conditional instruction that is not
executed because the condition is false, the ADSP-2106x still drives the
address and memory select for the write, but does not assert the write
strobe or drive any data.
5.5.2

Multiprocessor Memory

Timing for multiprocessor memory accesses is shown in Figure 5.19.
For complete information on multiprocessor memory accesses, see
"Direct Reads & Writes" and "Data Transfers Through The EPBx
Buffers" in the Multiprocessing chapter of this manual.
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