Program Sequencing
If nesting is not enabled, the processor masks out all interrupts and
IMASKP is not used, although IMASKP is still updated to create a
temporary interrupt mask.
IRPTL is updated, but the ADSP-2106x does not vector to an interrupt
that occurs while its service routine is already executing. It waits until
the RTI completes before vectoring to the service routine again.
3.6.6
Status Stack Save & Restore
For low-overhead interrupt servicing, the ADSP-2106x automatically
saves and restores the status and mode contexts of the interrupted
program. The three external interrupts (
and the VIRPT vector interrupt cause an automatic push of ASTAT
and MODE1 onto the status stack, which is five levels deep. These
registers are automatically popped from the status stack by the return
from interrupt instruction, RTI (and by the JUMP (CI) instruction,
described below in "Clearing The Current Interrupt For Reuse").
IRQ
Only
, timer, and VIRPT interrupts cause a push of the
2-0
status stack. All other interrupts require an explicit save and
restore of the appropriate registers to memory.
Pushing ASTAT and MODE1 preserves the status and control bit
settings so that if the service routine alters these bits, the original
settings are automatically restored upon the return from interrupt.
Note, however, that the FLAG
status stack pushes and pops; the values of these bits carry over from
the main program to the service routine and from the service routine
back to the main program.
The top of the status stack contains the current values of ASTAT and
MODE1. Reading and writing these registers does not move the stack
pointer. The stack pointer is moved, however, by explicit PUSH and
POP instructions.
3.6.7
Software Interrupts
The ADSP-2106x provides software interrupts that emulate interrupt
behavior but are activated through software instead of hardware.
Setting one of bits 28-31 in IRPTL, with either a BIT SET instruction or
a write to IRPTL, activates a software interrupt. The ADSP-2106x
branches to the corresponding interrupt routine if that interrupt is not
masked and interrupts are enabled.
www.BDTIC.com/ADI
IRQ
), the timer interrupt,
2-0
bits in ASTAT are not affected by
3-0
3
3 – 29
Need help?
Do you have a question about the ADSP-2106x SHARC and is the answer not in the manual?
Questions and answers