Timer Registers; Stack Flags - Analog Devices ADSP-2106x SHARC User Manual

3 Program Sequencing
Like other interrupts, the timer interrupt requires two cycles to fetch
and decode the first instruction of the service routine. The service
routine begins executing four cycles after the timer count reaches zero,
as shown in Figure 3.14.
CLOCK
TCOUNT = 1
PM
ADDRESS
Figure 3.14 Timer Interrupt Timing
3.7.3

Timer Registers

Both the TPERIOD and TCOUNT registers can be read and written by
universal register transfers. Reading the registers has no effect on the
timer. An explicit write to TCOUNT has priority over both the loading
of TCOUNT from TPERIOD and the decrementing of TCOUNT.
Neither TCOUNT nor TPERIOD are affected by a reset, so you should
initialize both registers after reset, before enabling the timer.
3.8

STACK FLAGS

The STKY status register maintains stack full and stack empty flags for
the PC stack as well as overflow and empty flags for the status stack
and loop stack. Unlike other bits in STKY, several of these flag bits are
not "sticky." They are set by the occurrence of the corresponding
condition and are cleared when the condition is changed (by a push,
pop, or processor reset).
STKY
Bit Name Definition
21 PCFL PC stack full
22 PCEM PC stack empty
23 SSOV Status stack overflow
24 SSEM Status stack empty
25 LSOV Loop stacks* overflow
26 LSEM Loop stacks* empty
3 – 36
* Loop address stack and loop counter stack
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NOP
TCOUNT = 0 (FETCH)
INTERRUPT
VECTOR
Not Sticky
Not sticky
Not sticky
Sticky
Not sticky
Sticky
Not sticky
NOP EXECUTE
(DECODE) FIRST
SERVICE
ROUTINE
INSTRUCTION
TIMER
Sticky/
Cleared By
Pop
Push
RESET
Push
RESET
Push