Processors-Take-Turns - Analog Devices ADSP-2106x SHARC User Manual

11 System Design
Figure 11.12 Multiple SHARCs Booting From One EPROM, Processors-Take-Turns
Figure 11.13 Multiple SHARCs Booting From One EPROM, One-Boots-Others
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ADDR
31-0
EBOOT
LBOOT
DATA
47-0
RD
ADSP-2106x
ACK
(S1, Master)
BMS
BMS ADDR
31-0
EBOOT
DATA
47-0
LBOOT
RD
ADSP-2106x
ACK
(S2, Slave)
BMS ADDR
31-0
EBOOT
DATA
47-0
LBOOT
RD
ADSP-2106x
ACK
(S6, Slave)
ADDR
31-0
EBOOT
LBOOT
DATA
47-0
RD
ADSP-2106x
(S1)
BMS
EBOOT ADDR
31-0
LBOOT
DATA
47-0
RD
ADSP-2106x
(S2)
BMS
EBOOT ADDR
31-0
LBOOT
DATA
47-0
RD
ADSP-2106x
BMS
(S6)
ADDR
DATA
23-16
DATA
RD
CS
EPROM
ADDR
DATA
23-16
DATA
RD
CS
EPROM
Here, multiple SHARCs boot
from the same EPROM. For
this configuration, the loader
routine uses a jump table to
indicate the address of the
image that loads into each
processor. The processors
can load the same image or
individual images.