Input Signal Conditioning - Analog Devices ADSP-2106x SHARC User Manual

11.4

INPUT SIGNAL CONDITIONING

The ADSP-2106x SHARC processor is a CMOS device. It has input
conditioning circuits which simplify system design by filtering or
latching input signals to reduce susceptibility to glitches or reflections.
The following sections describe why these circuits are needed and their
effect on input signals.
A typical CMOS input consists of an inverter with specific N and P
device sizes that cause a switching point of approximately 1.4V. This
level is selected to be the midpoint of the standard TTL interface
specification of V =0.8V and V
IL
unfortunately, has a fast response to input signals and external glitches
wider than about 1 ns. Glitch rejection circuits, filter circuits, and
hysteresis are therefore added after the input inverter on some
ADSP-2106x inputs, as described below.
11.4.1 Glitch Rejection Circuits
The SHARC processors have on-chip glitch rejection circuits that latch
certain input signals for a fixed time period after a transition has been
detected. The purpose of these circuits is to make the input less
sensitive to reflections and ringing once the first edge has been
received. Thus, the circuits will not provide any reduced immunity to
glitches that are randomly placed. The glitch rejection circuits are only
used on some signals that are used as strobes. These signals are:
read and write strobes
DMA request inputs
serial port clock inputs
The glitch rejection circuit will cause the input signal to be latched for
approximately 4 to 5 ns after a transition has been detected. Glitch
rejection circuits are not implemented on the SHARC's data, address,
or control lines that settle out normally before they are used. A glitch
rejection circuit is used on the processor's clock input (CLKIN).
11.4.2 Link Port Input Filter Circuits
The SHARC's link port input signals have on-chip filter circuits rather
than glitch rejection circuits. Filtering is not used on most signals since
it delays the incoming signal and therefore the timing specifications.
Filtering is implemented only on the link port data and clock inputs.
This is possible because the link ports are self-synchronized, i.e. the
clock and data are sent together. It is not the absolute delay but rather
the relative delay between clock and data that determines performance
margin.
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System Design
=2.0V. This input inverter,
IH
RD WR
,
DMAR1 DMAR2
,
RCLK0, RCLK1, TCLK0, RCLK1
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