Figure 6.6 Chain Pointer Register & Pci Bit - Analog Devices ADSP-2106x SHARC User Manual

The CP register is 18 bits wide, of which the lower 17 bits are the
memory address field. The memory address field is offset by
0x0002 0000 before it is used by the DMA controller. The most
significant bit (bit 17) of the CP register is a control bit called PCI
(Program-Controlled Interrupts). The PCI bit selects whether or not an
interrupt occurs at the completion of the current DMA sequence (in
addition to the interrupt's mask bit in IMASK). When PCI=1, the
corresponding DMA channel interrupt is enabled and will occur when
the count register reaches zero. When PCI=0, the channel's interrupt is
disabled. Note that the PCI bit only affects DMA channels for which
chaining is enabled (i.e. CHEN bit set to 1). For non-chained DMA
operations, the IMASK register must be used to disable the interrupt.
Interrupt requests enabled by the PCI bit can still be masked out (i.e.
disabled) in the IMASK register. Figure 6.6 illustrates the PCI bit
within the CPx register.
Caution: Because the PCI bit is not part of the memory address in the
CP register, care should be taken when writing and reading addresses
to and from the register. To prevent errors, it is a good practice to
mask out the PCI bit (bit 17) when copying the address in CP to
another address register.
17 16 15 14 13
CPx
PCI bit
Figure 6.6 Chain Pointer Register & PCI Bit
The general-purpose register (GP) can be useful during chained DMA
sequences. It is loaded from memory with the other parameter
registers, and can be used to point to the last DMA sequence that was
completed. This allows a program to determine where the last full (or
empty) data buffer is located. Since it is a general-purpose register
with no dedicated functionality, it can be used for any purpose.
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12 11 10 9 8 7 6 5
Memory Address Field
(address of next TCB)
DMA 6
4 3 2 1 0
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