Analog Devices ADSP-2106x SHARC User Manual page 693

Latency .................... 3-22, 11-44, 11-47, E-2,
......................................... E-27, E-36, E-39
LBOOT pin .............................................. 11-32
LCE condition ...... 3-7, 3-8, 3-13, 3-19, 3-20
LCNTR ... 3-5, 3-13, 3-19, 3-20, A-36, A-37
LCOM register ................... 6-52, 11-35, E-28
LCTL register ...................... 6-16, 6-17, 11-35
LEFTO ........................................................ 2-24
LEFTZ ........................................................ 2-24
Len6 field ................................................... 2-20
Level-sensitive interrupts ........................ 3-31
LEXT bit (LCTL register) ........................ E-26
Link Assignment Register (LAR)
Link buffer ...... 6-17, 9-2, 9-12, 9-16, 11-45,
..................... E-28, E-41, E-43, E-46, G-3
Link buffer 4 (LBUF4) ................ 11-34, 11-37
Link buffer DMA interrupts ................... 6-17
Link buffer status ........................... 9-16, E-45
Link port acknowledge .......................... 11-34
Link port control registers ..................... 11-47
Link port, disabling .................................. 9-12
Link port DMA channels ......................... 6-15
Link port, loopback .................................. 9-12
Link ports ....... 7-4, 7-7, 11-17, 11-21, 11-47
Link service request register
(LSRQ) ............................ 3-25, 9-7, 9-19
LOGB ............................................................ 2-6
Logical operations ...................................... 2-5
Loop abort (LA) ........... 3-9, 3-16, 3-18, A-5,
.................................................. A-28, A-30
Loop address stack ........ 3-5, 3-9, 3-13, 3-18
Loop count .................................................. 3-5
Loop counter ........................... 3-7, 3-15, A-6
Loop counter stack ............... 3-5, 3-18, 3-19,
................................................... 3-20, A-36
Loop nesting .............................................. 3-19
Loop reentry (LR) ............... 3-15, 3-30, A-34
Loop restrictions ............................. 3-14, 3-19
Loop stack ..... 3-18, 3-25, 3-36, A-28, A-38,
........................................ A-50, E-20, E-22
Loop stack push ........................................ 3-20
Loop termination ................... 3-7, 3-12, 3-14
Loop termination address ....................... 3-18
Loop termination condition ..................... 3-8,
........... 3-13, 3-15, 3-16, 3-17, 3-18, 3-19
Loopback ..................................... 10-37, 10-41
Loops .......................................................... 3-13
LP2I interrupt ............................................ 3-25
LP3I interrupt ............................................ 3-25
LRERRx bits (LCOM register) ................ 9-23
www.BDTIC.com/ADI
LSRQ interrupt ................................. 3-25, 9-5
LSRQ register ............................................ 9-20
M
M field ................. 5-11, 5-18, 8-9, 8-12, 8-16
M registers ........................................... 4-1, 4-5
MANT .................................................. 2-6, 2-7
Mantissa ............................................ 2-3, B-35
MASTER ..................... 6-12, 6-38, 6-40, 6-43
Master mode DMA . 6-12, 6-22, 6-33, 11-46
Memory access timing ............................. 5-48
Memory acknowledge (ACK) ...... 5-37, 5-39
9-12, E-46
Memory bank size .................................... 5-38
Memory banks ..................... 5-10, 5-38, E-32
Memory blocks ............ 3-6, 3-38, 5-3, 11-43
Memory buffer ............................................ 6-5
Memory columns ...................................... G-3
Memory select lines (MS3-0) .................. 5-36,
................................ 5-38, 5-39, 6-43, E-24
Memory spaces ....................................... 11-42
Memory-mapped peripheral ................ 11-11
Mesh multiprocessing ............................. 1-18,
.................................. 9-9, 9-10, 10-5, 10-6
MI flag .............................................. 2-15, 2-17
MIS flag ...................................................... 2-16
MMSWS bit (WAIT register) ................. 5-44,
.............................. 7-22, 7-25, 8-13, 11-46
MN flag ............................................ 2-15, 2-17
MODE1 register .................... 2-6, 2-15, 2-28,
................ 3-5, 3-7, 3-9, 3-21, 3-22, 3-29,
................................. 4-4, 7-10, E-14, E-54
MODE2 register .......... 3-5, 3-31, 3-33, 3-41,
....................................... 11-12, E-16, E-55
Modified Harvard architecture ................ 5-3
Modify register (IMx) .............................. 6-21
Modulo addressing ................... 1-9, 4-4, 4-6
MOS flag .......................................... 2-16, 2-17
MR register (background) ....................... 2-12
MR register sets ........................................ 2-12
MR register transfers ....................... 2-13, B-1
MR registers ................................... 11-42, A-1
MR saturation ........................................... 2-14
MR0 register ......................... 2-12, 2-14, 2-16
MR1 register ......................... 2-12, 2-14, 2-17
MR2 register .................................... 2-12, 2-17
MR2B, MR1B, MR0B ................................ 2-18
MR2F, MR1F, MR0F ................................. 2-18
MS flag ......................................................... 3-8
MSGR0-MSGR7 registers .............. 7-32, 8-31
Index
X – 7