Bit Data Packing - Analog Devices ADSP-2106x SHARC User Manual

8 Host Interface
Figure 8.a shows how different data word sizes are transferred over
the external port.
47 40
32-Bit Float or Fixed,
32-Bit Packed
Figure 8.a External Port Data Alignment
8.5.3

32-Bit Data Packing

For a 16-bit host bus, the incoming data is latched on DATA
Similarly, outgoing data is driven on DATA
equal to zeroes. The sequence of events for 32-bit packing/unpacking
is different for writes and reads, as described below. For a 16-bit host
bus, the endian format of the transfers is controlled by the HMSWF bit
in the SYSCON register. If HMSWF=0, the least significant 16-bit word
will be packed first. If HMSWF=1, the most significant 16-bit word will
be packed first.
When a host reads a 32-bit word with 16-bit unpacking, using the
typical bus interface hardware shown in Figure 8.8 (at the end of this
chapter), the following sequence of events occurs (as illustrated in
Figure 8.5):
• The host initiates a read cycle by driving an address, asserting
the access is asynchronous, and asserting
• The selected ADSP-2106x deasserts REDY, latches the address, and
performs an internal direct read to get the data.
• When the ADSP-2106x has the data, it asserts REDY and drives the
1st 16-bit word.
• The host latches the data and deasserts
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DATA
47-0
32 24 16
EPROM
Boot
16-Bit Packed
D31 - D0,
40-Bit Extended Float
Instruction Fetch
8 0
.
31-16
with the other lines
31-16
CS
RD
(low).
RD
(high).
if