Table 5.8 Wait Register Bit Definitions - Analog Devices ADSP-2106x SHARC User Manual

Bit(s) Name
1-0 EB0WM
4-2 EB0WS
6-5 EB1WM
9-7 EB1WS
11-10 EB2WM
14-12 EB2WS
16-15 EB3WM
19-17 EB3WS
21-20 UBWM
24-22 UBWS
27-25 PAGSZ
28 PAGEIS
29 MMSWS
30 HIDMA
31 reserved

Table 5.8 WAIT Register Bit Definitions

* Wait state mode:
EBxWM Wait State Mode
00 External acknowledge only (ACK)
01 Internal wait states only
10 Both internal and external acknowledge required
11 Either internal or external acknowledge sufficient
** Number of wait states:
# of Bus
Wait Idle
EBxWS States Cycle?
000 0 no
001 1 yes
010 2 yes
011 3 yes
100 4 no
101 5 no
110 6 no
111 0 yes
Note that the bus idle cycle or hold time cycles will occur if
programmed, regardless of the waitstate mode. For example, the
ACK-only waitstate mode may have a hold time cycle
programmed for it.
†† Setting the HIDMA bit to 1 causes an idle cycle to be inserted after
every read (with
This allows a device with a slow tristate time to get off the local bus before
the next ADSP-2106x access begins. The idle cycle is inserted for every read
from the DMA latch, not just for a changeover. See "DMA Hardware
Interfacing" in the "External Port DMA" section of the DMA chapter for an
example showing an external DMA latch.
www.BDTIC.com/ADI
Function
External Bank 0 wait state mode*
External Bank 0 number of wait states**
External Bank 1 wait state mode*
External Bank 1 number of wait states**
External Bank 2 wait state mode*
External Bank 2 number of wait states**
External Bank 3 wait state mode*
External Bank 3 number of wait states**
Unbanked memory wait state mode*
Unbanked memory number of wait states**
Page size for DRAM (only in Bank 0) †
Single idle cycle on DRAM page boundary crossing
Single wait state for Multiprocessor Memory Space access
Single idle cycle for DMA handshake ††
Hold
Time
Cycle?
no
no
no
no
yes
yes
yes
no
DMAG
DMAG
x asserted) from an external DMA latch.
Memory
† DRAM page size:
PAGSZ DRAM Page Size
000 256 words
001 512 words
010 1024 words (1K)
011 2048 words (2K)
100 4096 words (4K)
101 8192 words (8K)
110 16384 words (16K)
111 32768 words (32K)
(See "DRAM Page Boundary Detection"
for more information on DRAM control.)
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