Instruction Cycle; Program Flow Variations - Analog Devices ADSP-2106x SHARC User Manual

3 Program Sequencing
Address: n
Instruction
n+1
Instruction
n+2
Instruction
n+3
Instruction
n+4
Instruction
n+5
Instruction
Linear Flow
CALL
Instruction
Instruction
Instruction
Instruction
Instruction
RTS
Subroutine
Figure 3.1 Program Flow Variations
3.1.1

Instruction Cycle

The ADSP-2106x processes instructions in three clock cycles:
• In the fetch cycle, the ADSP-2106x reads the instruction from either the
on-chip instruction cache or from program memory.
• During the decode cycle, the instruction is decoded, generating
conditions that control instruction execution.
• In the execute cycle, the ADSP-2106x executes the instruction; the
operations specified by the instruction are completed.
3 – 2
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DO UNTIL
Instruction
Instruction
N Times
Instruction
Instruction
Instruction
Loop
INTERRUPT
Instruction
Instruction
Instruction
Instruction
Instruction
Instruction
RTI
Interrupt
JUMP
Instruction
Instruction
Instruction
Instruction
Instruction
Jump
IDLE
Instruction
Instruction
Instruction
Instruction
Instruction
Idle