Register File - Analog Devices ADSP-2106x SHARC User Manual

Computation Units

Register File

Multiplier
Any Register
Figure 2.9 Input Registers For Multifunction Computations (ALU & Multiplier)
2.9 REGISTER FILE
The register file provides the interface between the processor's internal
data buses and the computation units. It also provides local storage for
operands and results. The register file consists of 16 primary registers and
16 alternate (secondary) registers. All of the data registers are 40 bits wide.
32-bit data from the computation units is always left-justified; on register
reads, the eight LSBs are ignored, and on writes, the eight LSBs are written
with zeros.
Program memory data accesses and data memory accesses to the register
file occur on the PM Data bus and DM Data bus, respectively. One PM
Data bus and/or one DM Data bus access can occur in one cycle. Transfers
between the register file and the 40-bit DM Data bus are always 40 bits
wide. The register file transfers data to and from the 48-bit PM Data bus in
the most significant 40 bits, writing zeros in the lower eight bits on
transfers to the PM Data bus.
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R0 - F0
R1 - F1
R2 - F2
R3 - F3
R4 - F4
R5 - F5
R6 - F6
R7 - F7
Any Register
R8 - F8
R9 - F9
R10 - F10
R11 - F11
ALU
R12 - F12
R13 - F13
R14 - F14
R15 - F15
2
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