External Memory Write - Overlays & I/O Memory; Memory Interface Summary (All Processors) - Analog Devices adsp-2100 Manual

external signals:
(deasserted), and the address and data buses are tristated.
10.6.7 External Memory Write – Overlays & I/O Memory
External memory writes may access either PM overlays, DM overlays, or I/O
memory space. These read operations occur in the following sequence (see
Figure 10.35):
1) The ADSP-2181 executes a write to an external memory address; the address
is driven on the address bus, data is driven on the data bus, and
BMS IOMS
, or
how it is configured.)
2) The external peripheral stores the data.
3) The ADSP-2181 stops driving the address and data buses and deasserts
CLKOUT
A0 – A13
DMS, PMS,
BMS, IOMS,
or CMS
WR
DATA
Figure 10.35 External Memory Write Timing
RD
remains high (deasserted) throughout the external memory write
operation.
10.7

MEMORY INTERFACE SUMMARY (ALL PROCESSORS)

Table 10.5 summarizes the states of the memory interface pins for various
combinations of program memory and data memory accesses. Table 10.6
summarizes the states of the memory interface and control pins during
reset, booting (ADSP-21xx boot memory booting, not ADSP-2181 byte
memory booting), and bus grant.
Memory Interface
PMS DMS IOMS BMS
, , ,
WR
, and is asserted. (
CMS RD WR
, , , and
CMS
may also be asserted, depending
10
remain high
PMS DMS
, ,
WR
.
10 – 37