Stack Status Register (Sstat) - Analog Devices adsp-2100 Manual

Each of the bits is automatically updated when a new status is generated
by an arithmetic instruction. Each bit is affected only by a subset of
arithmetic operations, as defined by the following table:
Status Bit
AZ, AN, AV, AC
AS
AQ
MV
SS
Arithmetic status is latched into ASTAT at the end of the cycle in which it
was generated, and cannot be used until the next cycle.
Loading any ALU, MAC, or Shifter input or output registers directly from
the DMD bus does not affect any of the arithmetic status bits. Executing
the ALU instruction PASS sets the AZ and AN bits for a given X or Y
operand and clears AC.
3.5.2

Stack Status Register (SSTAT)

The SSTAT register is eight bits wide and holds information about the four
processor stacks. The individual bits of SSTAT are defined as shown in
Figure 3.5. All of the bits are positive sense (1=true, 0=false).
7 6 5 4 3
0 1 0 1 0
Figure 3.5 SSTAT Register (Read-Only)
Program Control
Updated by
Any ALU operation except DIVS, DIVQ
ALU absolute value operation (ABS)
ALU divide operations (DIVS, DIVQ)
Any MAC operation except saturate MR (SAT MR)
Shifter EXP operation
2 1 0
1 0 1
PC Stack Empty
PC Stack Overflow
Count Stack Empty
Count Stack Overflow
Status Stack Empty
Status Stack Overflow
Loop Stack Empty
Loop Stack Overflow
3
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