Analog Devices adsp-2100 Manual page 237

10 Memory Interface
Figure 10.23 shows the external memory buses and control signals in an
ADSP-2181 system. Two control lines determine the direction of external
memory transfers:
for a write operation. Typically, you would connect
Enable) and
Internal memory accesses do not drive any external signals:
,
BMS IOMS
data buses are tristated.
1/2x CLOCK
or
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
SYSTEM
INTERFACE
or
µCONTROLLER
16
Figure 10.23 ADSP-2181 System Diagram
10 – 24
is active low signaling a read and
RD
to (Write Enable) of your memory.
WR WE
, , and remain high (deasserted), and the address and
RD WR
ADSP-2181
CLKIN
ADDR
XTAL
FL0-2
PF0-7
DATA
IRQ2
IRQE
IRQL0
IRQL1
SPORT 1
SCLK1
RFS1 or IRQ0
TFS1 or IRQ1
DT1 or FO
DR1 or FI
SPORT 0
SCLK0
RFS0
TFS0
DT0
DR0
IDMA PORT
IRD
IWR
IS
IAL
IACK
PWDACK
IAD15-0
14
13-0
24
23-0
BMS
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
is active low
WR
to (Output
RD OE
,
PMS DMS
A 13-0
A0-A21
D 23-16
BYTE
MEMORY
D 15-8
DATA
CS
A 10-0
ADDR
I/O SPACE
D 23-8
(PERIPHERALS)
DATA
2048 Locations
CS
A 13-0
ADDR
OVERLAY
D 23-0
MEMORY
DATA
PM Segments
DM Segments
,
Two 8K
Two 8K