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MISC
15
MODE CONTROL
The AR saturation mode bit, (AR_SAT), when set to 1, causes the AR
register to saturate if an ALU operation causes an overflow, as described
in Chapter 2, "Computation Units."
The MAC result placement mode (M_MODE) determines whether or not
the left shift is made between the multiplier product and the MR register.
Setting the Timer Enable bit (TIMER) starts the timer decrementing logic.
Clearing it halts the timer.
The GO mode (G_MODE) allows an ADSP-21xx processor to continue
executing instructions from internal memory (if possible) during a bus
grant. The GO mode allows the processor to run; only if an external
memory access is required does the processor halt, waiting for the bus to
be released.
Instruction Format:
Mode Control, Instruction Type 18:
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
TI:
Timer Enable
AS: AR Saturation Mode Control
BR:
Bit Reverse Mode Control
GM: GO Mode
15 – 88
0
0
1
1
0
0
TI
MM
AS
MM: Multiplier Placement
OL: ALU Overflow Latch Mode
Control
SR:
Secondary Register Bank
Mode
OL
BR
SR GM
0 0
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