Analog Devices adsp-2100 Manual page 483

EXP ...................................................................... 2-33
EXPADJ .............................................................. 2-29
Exponent compare logic .................................. 2-22
Exponent detector ........................... 2-22, 2-26, 2-27
External address bus ................................... 1-3, 1-8
External clock ............................................. 5-8, 9-21
External data bus ......................................... 1-3, 1-8
External interrupts ............................................ 9-14
External memory ..................................... 5-38, 10-2
External SCLK ..................................................... 5-8
Extra cycles ...................................................... 15-18
EZ-ICE emulator ............................................. 11-26
F
Fast fourier transform (FFT) ................. 14-1, 14-11
Fast start-up ....................................................... 9-22
FIR filter .................................................... 14-1, 14-4
Flag In (FI) ............................................ 1-9, 3-24, 9-1
Flag Out (FO) ................................................ 1-9, 9-1
Flag pins ............................................................. 9-15
Floating-point .................................................... 2-33
Fractional mode ........ 2-2, 2-3, 3-23, 3-24, C-1, C-4
Frame synchronization .. 5-2, 5-5, 5-10, 5-11, 5-12,
........................................ 5-14, 5-15, 5-30, 5-34, 9-23
Framing ....................................................... 5-3, 5-16
Full duplex operation ....................................... 5-34
G
GO mode .......................................... 3-23, 3-24, 5-38
H
HACK ..................................................... 7-3, 7-7, 7-9
Harvard architecture ................................. 1-2, 10-1
HDR overwrite mode .................................. 7-7, 7-9
HDR registers ................................ 7-4, 7-5, 7-6, 7-7
HI-extend (HIX) ....................................... 2-26, 2-36
HI/LO reference signal ........................... 2-22, 2-24
HIP configuration modes .................................. 7-3
HIP data registers ................ 3-15, 7-4, 7-5, 7-6, 7-7
HIP during powerdown .................................. 9-24
HIP interrupt ........................... 3-18, 7-9, 7-10, 7-11
HIP pin summary ............................................... 7-2
HIP read interrupt .............................................. 7-4
HIP status registers ............................................. 7-6
HIP status synchronization ............................... 7-8
HIP timing ............................. 7-12, 7-13, 7-14, 7-15
HIP write interrupt ............................................. 7-4
HMASK register ............ 3-15, 7-4, 7-10, 7-11, 12-8
HMD0 ............................................................ 7-3, 7-4
HMD1 ................................................................... 7-4
Hold offs .......................................................... 11-25
Host ....................................................................... 1-2
Host data bus ....................................................... 7-4
Host handshaking ............................................... 7-7
Host interface port (HIP) ... 1-2, 1-9, 3-15, 7-1, 7-4,
............................................... 9-4, 10-15, 12-2, 13-13
Host interface timing ........................................ 7-11
Host read strobe .................................................. 7-4
Host write strobe ................................................ 7-4
HSEL ..................................................................... 7-3
HSIZE .......................................................... 7-3, 7-11
HSR registers .......................................7-4, 7-5, 9-25
I
I registers ..................4-2, 4-3, 5-26, 5-28, 8-14, 12-2
IACK ...........................................11-12, 11-13, 11-25
ICNTL register .... 3-14, 3-15, 3-16, 3-20, 9-14, 12-4
IDLE instruction ..................... 3-7, 3-10, 5-26, 9-15,
...........................................................9-19, 9-26, 9-30
IDMA ..................................................... 11-12, 15-18
IDMA booting ................................................. 11-24
IDMA control register ..............11-14, 11-15, 11-16
IDMA hold offs ............................................... 11-25
IFC register ............................ 3-14, 3-18, 3-20, 12-4
IIR filter ..................................................... 14-1, 14-6
IMASK register .................... 3-14, 3-15, 3-16, 3-19,
........................................ 3-20, 7-10, 8-12, 9-14, 12-4
Immediate shifts ............................................... 2-30
Indirect addressing .............................1-8, 4-3, 12-2
Indirect jumps ................................................... 12-2
Input formats ..................................................... 2-18
Input registers ..................................................... 1-7
Instruction completion latencies ......... 5-38, 15-18
Instruction set ............................................ 15-1, A-1
Integer ............................................... 3-23, 3-24, C-1
Integer mode ............................................... 2-3, C-4
Internal buses ...................................................... 1-8
Internal memory ................................................. 1-2
Internal oscillator .............................................. 9-22
Interrupt control register ................................. 3-15
Interrupt controller .............................3-1, 3-3, 3-11
Interrupt force & clear register .............. 3-15, 3-18
Interrupt latencies .................................... 3-19, 5-42
Interrupt mask register .................................... 3-16
Interrupt nesting ............................................... 3-16
Interrupt request ...............................5-40, 9-1, 9-14
Interrupt sensitivity .......................................... 9-14
Index
X – 3