Analog Devices adsp-2100 Manual page 486

Index
Shifter arithmetic ................................................ 2-3
Shifter array ....................................................... 2-22
Shifter input/output registers ........................ 2-28
Shifter operations .............................................. 2-28
Shifter sign ......................................................... 2-26
SI register .................................................. 2-22, 2-23
Signed numbers .................................................. 2-1
Sine approximation .......................................... 14-7
SLEN ....................................... 5-10, 5-16, 5-31, 5-32
Software examples ............................................ 14-1
Software reboot ............................................... 10-16
SPORT .......................... 1-8, 3-18, 5-1, 5-3, 5-6, 9-23
SPORT control register ......... 5-8, 5-10, 5-11, 5-13,
................................................. 5-14, 5-16, 5-23, 5-31
SPORT enable ...................................................... 5-7
SPORT interrupts .............................. 5-3, 5-34, 5-41
SPORT multichannel frame delay .................. 5-31
SPORT programming ......................................... 5-4
SPORT timing .................................................... 5-34
SPORT configuration ......................................... 5-5
SPORT0 ............................ 5-1, 5-5, 5-15, 5-16, 5-30,
................................................. 8-13, 12-7, 13-6, 13-7
SPORT0 configuration registers ....................... 5-5
SPORT0 control register .................................. 5-30
SPORT0 multichannel word enable registers . 5-32
SPORT1 ............................................... 5-5, 5-30, 8-9,
................................................. 8-13, 9-14, 9-15, 12-2
SPORT1 alternate configuration ....................... 5-8
SPORT1 configuration registers ....................... 5-5
SR register ................................................. 2-22, 2-23
SR0 register ............................................... 2-22, 2-24
SR1 register ............................................... 2-22, 2-24
SSTAT ................................................................. 12-5
Stacks ........................................................... 3-4, 12-5
Start-up delay .................................................... 9-20
Start-up time ...................................................... 9-21
Startup timing ................................................... 5-38
Status bits .................................................. 3-21, 12-5
Status condition ......................................... 3-6, 3-25
Status logic ........................................................... 3-4
Status registers ......................................... 3-15, 3-20
Status stack ............................ 3-16, 3-20, 3-22, 12-5
Stolen cycles ..................................................... 15-18
Subroutine ........................................................... 3-9
Subtract with borrow ......................................... 2-8
Synchronization delay ....................................... 9-3
Synchronization (serial clk to processor clk) ... 5-38
System Builder .................................................. 1-10
System Control Register ........................ 9-14, 9-15,
........................................................ 10-17, 15-12, E-1
System interface .................................................. 9-1
X – 6
T
T1 interface ........................................................ 5-31
TCOUNT ............................... 6-1, 6-2, 6-3, 6-4, 12-6
TDV ..................................................................... 5-32
Termination condition .............................. 3-6, 3-10
TFS ............................................ 5-2, 5-11, 5-12, 5-30
TFS0 .................................................................... 5-30
TFSR ........................................................... 5-10, 5-11
TFSW .................................................................. 5-13
Time-division multiplexed .............................. 5-30
Timer .............. 3-18, 3-23, 3-24, 6-1, 9-5, 12-2, 12-6
Timer interrupt .......................................... 3-19, 6-1
Timer operation .................................................. 6-3
Timer registers ............................................. 6-1, 6-2
TOPPCSTACK ..3-4, 3-25, 3-26, 3-27, 15-84, 15-85
TPERIOD ............................... 6-1, 6-2, 6-3, 6-4, 12-6
Transmit data valid .......................................... 5-32
Transmit frame sync ................................ 5-11, 5-12
Transmit interrupt (SPORT) ..................... 5-4, 5-36
Transmit register ................................................. 5-6
Transmit word enables .................................... 5-32
Transmitting data ............................................... 5-6
TSCALE ................................. 6-1, 6-2, 6-3, 6-4, 12-6
Twos-complement ........... 2-1, 2-18, 2-33, C-1, C-4
TX register ............................................5-2, 5-4, 5-35
TX0 register .......................................................... 5-6
TX1 register .......................................................... 5-6
U
Underflows .......................................................... 2-8
Unsigned ............................................. 2-1, 2-18, C-1
W
Word length .........................................5-3, 5-9, 5-32
Write enable ....................................................... 10-3
Write operation ............................................... 15-12
X
XTAL pin ............................................9-1, 9-21, 9-22
XTALDELAY ............................................ 9-18, 9-20
XTALDIS ............................................................ 9-18
Z
Zero-overhead looping ............................... 1-5, 3-1