Analog Devices adsp-2100 Manual page 67

Adsp-2100 family programmable single-chip microprocessors
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At this point, there are three possible results depending on the type of
instruction at the end of the loop. Case 1 illustrates the most typical
situation. Cases 2 and 3 are also allowed but involve greater program
complexity for proper execution.
Case 1
If the last instruction in the loop is not a jump, call, return, or idle, the
next address circuit will select the next address based on the
termination condition stored on the top of the loop stack. If the
condition is false, the top address on the PC stack is selected, causing
a fetch of the first instruction of the loop. If the termination condition
is true, the PC incrementer is chosen, causing execution to fall out of
the loop. The loop stack, PC stack, and counter stack (if being used)
are then popped.
(Note that conditional arithmetic instructions execute based on the
condition explicitly stated in the instruction, whereas the loop
sequencing is controlled by the (implicit) termination condition
contained on top of the stack.)
Case 2
If the last instruction in the loop is a jump, call, or return, the
explicitly stated instruction takes precedence over the implicit
sequencing of the loop. If the condition in the instruction is false,
normal loop sequencing takes place as described for Case 1.
If the condition in the instruction is true, however, program control
transfers to the jump/call/return address. Any actions that would
normally occur upon an end-of-loop detection do not take place:
fetching the first instruction of the loop, falling out of the loop and
popping the loop stack, PC stack, and counter stack, or decrementing
the counter.
(Note that for a return instruction, control is passed back to the top of
the loop since the PC stack contains the beginning address of the
loop.)
Case 3
If the last instruction in the loop is an IDLE, program flow is
controlled by the IDLE instruction rather than the loop. When the
IDLE instruction is executed, the processor enters a low-power wait-
for-interrupt state. When the processor is interrupted, loop execution
terminates and program execution continues with the first instruction
following the loop.
Program Control
3
3 – 7

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