Analog Devices adsp-2100 Manual page 419

MULTIFUNCTION
15
COMPUTATION with REGISTER to REGISTER MOVE
Syntax:
Permissible dregs
AX0
AX1
AY0
AY1
AR
Description:
transfer. The contents of the source are always right-justified in the
destination register after the read.
The computation must be unconditional. All ALU, MAC and Shifter
operations are permitted except Shift Immediate and ALU DIVS and
DIVQ instructions.
The fundamental principle governing multifunction instructions is that
registers (and memory) are read at the beginning of the processor cycle
and written at the end of the cycle. The normal left-to-right order of
clauses (computation first, register transfer second) is intended to imply
this. In fact, you may code this instruction with the order of clauses
reversed. The assembler produces a warning, but the results are identical
at the opcode level. If you turn off semantics checking in the assembler (–s
switch) the warning is not issued.
Because of the read-first, write-second characteristic of the processor,
using the same register as source in one clause and a destination in the
other is legal. The register supplies the value present at the beginning of
the cycle and is written with the new value at the end of the cycle.
For example,
(1) AR = AX0 + AY0, AX0 = MR1;
is a legal version of this multifunction instruction and is not flagged by the
assembler. Reversing the order of clauses, as in
(2) AX0 = MR1, AR = AX0 + AY0;
15 – 96
<ALU>
<MAC>
<SHIFT>
MX0 SI
MX1 SE
MY0 SR0
MY1 SR1
MR0
MR1
MR2
Perform the designated arithmetic operation and data
, dreg = dreg ;