Rounding Mode - Analog Devices adsp-2100 Manual

2 Computational Units

2.3.2.6 Rounding Mode

The accumulator has the capability for rounding the 40-bit result R at the
boundary between bit 15 and bit 16. Rounding can be specified as part of
the instruction code. The rounded output is directed to either MR or MF.
When rounding is invoked with MF as the output register, register
contents in MF represent the rounded 16-bit result. Similarly, when MR is
selected as the output, MR1 contains the rounded 16-bit result; the
rounding effect in MR1 affects MR2 as well and MR2 and MR1 represent
the rounded 24-bit result.
The accumulator uses an unbiased rounding scheme. The conventional
method of biased rounding is to add a 1 into bit position 15 of the adder
chain. This method causes a net positive bias since the midway value
(when MR0=0x8000) is always rounded upward. The accumulator
eliminates this bias by forcing bit 16 in the result output to zero when it
detects this midway point. This has the effect of rounding odd MR1 values
upward and even MR1 values downward, yielding a zero large-sample
bias assuming uniformly distributed values.
Using x to represent any bit pattern (not all zeros), here are two examples
of rounding. The first example is the typical rounding operation.
Example 1
Unrounded value:
Bit 15 = 1
Add 1 to bit 15 and carry
Rounded value:
The compensation to avoid net bias becomes visible when the lower 15
bits are all zero and bit 15 is one, i.e. the midpoint value.
2 – 20
MR2 MR1
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MR0
1