Analog Devices adsp-2100 Manual page 482

Index
Branching ............................................................. 3-1
BTYPE ................................................................. 11-9
Buffer length ........................................................ 4-5
Bus exchange ...............1-5, 1-8, 2-15, 4-1, 4-9, 12-6
Bus grant (BG) ........................................... 3-18, 9-15
Bus request (BR) ................ 5-38, 10-15, 10-21, 13-2
Buses .............................................................. 1-3, 1-8
BWAIT .............................................................. 10-17
BWCOUNT ............................................... 9-13, 11-7
Byte memory ..................................................... 11-9
C
C Compiler ........................................................ 1-10
C language ......................................................... 14-3
CALL ............................................ 3-4, 3-8, 3-9, 3-24
Carry (AC) .......................... 2-2, 2-5, 2-8, 2-13, 2-36
Carry-in (CI) ........................................................ 2-5
Chip enable ........................................................ 10-3
Circular buffer addressing ... 1-5, 1-7, 4-1, 4-3, 4-8
CLKIN ....................................................9-1, 9-3, 9-4
CLKOUT ...................................... 9-2, 9-3, 9-4, 10-2
Clock frequency .................................................. 8-9
Clock signals ........................................................ 9-1
Clock synchronization (SPORT) ..................... 5-35
Clock synchronization delay (SPORT) .......... 5-34
CNTR register .....................................3-4, 3-9, 12-4
Codec interface .................................................. 13-5
Companding .................... 1-2, 5-5, 5-15, 5-23, 5-24,
........................................ 5-25, 5-32, 5-36, 5-37, 5-42
Computation with data register move .......... 15-7
Computation with memory read ................... 15-6
Computation with memory write .................. 15-6
Computational units .............. 1-6, 3-23, 12-1, 12-6
Condition ........................................................... 3-20
Condition logic .................................................... 3-3
Conditional instructions .................................. 3-24
Configuring interrupts ..................................... 3-14
Context reset ...................................................... 11-7
Context switching ............................................. 3-12
Continuous transmission ................................. 5-20
Control/status registers ........................... 1-12, E-1
Core architecture ................................................. 1-5
Count stack ..........................................3-4, 3-5, 12-5
Counter expired (CE) ...........................3-4, 3-6, 3-9
Cycle stealing .................................................. 11-25
X – 2
D
D/A .................................................................. 10-14
DAC ...................................................................... 1-3
DAC interface .................................................... 13-8
DAG1 ....................................................1-7, 4-2, 12-2
DAG2 .............................. 1-7, 3-3, 3-4, 3-8, 4-2, 12-2
Data address generators ........................... 4-1, 12-2
Data bus ............................................................... 4-1
Data memory .......................................1-7, 1-8, 10-1
Data memory address bus .......................... 1-3, 1-8
Data memory data bus ................................ 1-3, 1-8
Data memory interface .................................. 10-10
Data memory read ............................................ 15-6
Data structures .................................................... 4-7
Data transfer ........................................................ 4-1
Denormalization ................................................. 1-6
Denormalize ...................................................... 2-31
Derive block exponent ..................................... 2-29
Derive exponent ....................................... 2-22, 2-26
Development tools ............................................ 14-2
Digital-to-analog conversion ........................... 13-5
Direct addressing ................................................ 1-8
Divide primitives ................................................ 2-9
Division exceptions ............................................ B-1
Division ................................................................ 2-9
DIVQ .................................................. 2-10, 2-11, B-1
DIVS .............................................. 2-2, 2-9, 2-10, B-1
DMA ................................................................. 15-18
DMA bus ..................................................... 1-8, 10-1
DMD bus ................................... 1-8, 2-19, 2-22, 3-4,
................................................... 3-5, 3-20, 4-10, 10-1
DMD-PMD bus exchange ........ 2-15, 4-1, 4-9, 4-10
DMOVLAY ...................................................... 10-31
DMS ........................................................................ 1-8
DO UNTIL ........... 3-4, 3-5, 3-6, 3-8, 3-9, 3-12, 12-5
DR input ...................................................... 5-2, 5-36
dreg ........................................................ 15-12, 15-14
DT output ............................................................. 5-2
Dual operand fetches ........................... 1-2, 1-5, 1-7
E
Edge-sensitive .................................3-15, 3-16, 3-18
Edge-sensitive interrupts ................................. 9-14
End-of-loop ................................................. 3-7, 3-10
EPROM ...................................................... 1-4, 10-17