Status Registers & Status Stack; Arithmetic Status Register (Astat) - Analog Devices adsp-2100 Manual

3 Program Control
3.5
Processor status and mode bits are maintained in internal registers which
can be independently read and written over the DMD bus. These registers
are:
ASTAT
SSTAT
MSTAT Mode status register
ICNTL
IMASK
IFC
The interrupt-configuring status registers are described in the previous
section. ASTAT, SSTAT, and MSTAT are discussed in the following
sections.
The current ASTAT, MSTAT, and IMASK values are pushed onto the
status stack when the processor responds to an interrupt; they are popped
upon return from the interrupt service routine (with the RTI instruction).
The depth of the stack varies from processor to processor. In each case,
sufficient stack depth is provided to accommodate nesting of all
interrupts.
3.5.1
ASTAT is eight bits wide and holds the status information generated by
the computational blocks of the processor. The individual bits of ASTAT
are defined as shown in Figure 3.4. The bits which express a particular
condition (AZ, AN, AV, AC, MV) are all positive sense (1=true, 0=false).
7 6
0 0
SS MV AQ
3 – 20
Figure 3.4 ASTAT Register
STATUS REGISTERS & STATUS STACK
Arithmetic status register
Stack status register(read-only)
Interrupt control register
Interrupt mask register
Interrupt force/clear register(write-only)

Arithmetic Status Register (ASTAT)

5 4 3 2 1 0
0 0 0 0 0 0
AS AC AV AN AZ
ALU Result Zero
ALU Result Negative
ALU Overflow
ALU Carry
ALU X Input Sign
ALU Quotient
MAC Overflow
Shifter Input Sign